Searched refs:req (Results 26 - 50 of 159) sorted by relevance

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/gem5/src/kern/freebsd/
H A Dfreebsd.hh80 isTtyReq(unsigned req) argument
82 switch (req) {
/gem5/src/arch/arm/
H A Dlocked_mem.hh94 handleLockedRead(XC *xc, const RequestPtr &req) argument
96 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
99 req->getPaddr());
114 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
116 if (req->isSwap())
120 xc->getCpuPtr()->name(), req->getPaddr());
125 if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
128 req->setExtraData(0);
H A Dtlb.hh75 * @param req Request requiring a translation.
80 virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
234 Fault getTE(TlbEntry **te, const RequestPtr &req,
239 Fault getResultTe(TlbEntry **te, const RequestPtr &req,
244 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
245 Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
247 bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
301 Fault trickBoxCheck(const RequestPtr &req, Mode mode,
331 Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
334 translateFunctional(const RequestPtr &req,
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H A Dstage2_mmu.hh75 RequestPtr req; member in class:ArmISA::Stage2MMU::Stage2Translation
90 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
96 req->setVirt(0, vaddr, size, flags, masterId, 0);
101 parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
H A Dtlb.cc136 TLB::finalizePhysical(const RequestPtr &req, argument
139 const Addr paddr = req->getPaddr();
142 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
143 req->setPaddr(GenericISA::iprAddressPseudoInst(
565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, argument
569 Addr vaddr_tainted = req->getVaddr();
575 Request::Flags flags = req->getFlags();
581 assert(flags & MustBeOne || req->isPrefetch());
599 req->setPaddr(paddr);
601 return finalizePhysical(req, t
605 checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode) argument
783 checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc) argument
1016 checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode) argument
1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument
1200 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) argument
1221 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) argument
1242 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType) argument
1259 translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType, bool callFromS2) argument
1452 getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) argument
1519 getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) argument
1603 testTranslation(const RequestPtr &req, Mode mode, TlbEntry::DomainType domain) argument
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H A Dstage2_lookup.cc60 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
70 fault = stage2Tlb->checkPermissions64(stage2Te, req, mode, tc);
72 fault = stage2Tlb->checkPermissions(stage2Te, req, mode);
75 mergeTe(req, mode);
82 Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode) argument
179 Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req, argument
185 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
191 mergeTe(req, mode);
/gem5/src/mem/
H A Dabstract_mem.cc212 const RequestPtr &req = pkt->req; local
213 Addr paddr = LockedAddr::mask(req->getPaddr());
221 if (i->matchesContext(req)) {
223 req->contextId(), paddr);
231 req->contextId(), paddr);
232 lockedAddrList.push_front(LockedAddr(req));
243 const RequestPtr &req = pkt->req; local
244 Addr paddr = LockedAddr::mask(req
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H A Dpacket.hh329 RequestPtr req; variable
714 inline MasterID masterId() const { return req->masterId(); }
766 AtomicOpFunctor *getAtomicOp() const { return req->getAtomicOpFunctor(); }
767 bool isAtomicOp() const { return req->isAtomic(); }
799 : cmd(_cmd), id((PacketId)_req.get()), req(_req),
804 if (req->hasPaddr()) {
805 addr = req->getPaddr();
807 _isSecure = req->isSecure();
809 if (req->hasSize()) {
810 size = req
879 makeReadCmd(const RequestPtr &req) argument
895 makeWriteCmd(const RequestPtr &req) argument
915 createRead(const RequestPtr &req) argument
921 createWrite(const RequestPtr &req) argument
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H A Dpage_table.cc157 EmulationPageTable::translate(const RequestPtr &req) argument
160 assert(pageAlign(req->getVaddr() + req->getSize() - 1) ==
161 pageAlign(req->getVaddr()));
162 if (!translate(req->getVaddr(), paddr))
163 return Fault(new GenericPageTableFault(req->getVaddr()));
164 req->setPaddr(paddr);
165 if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
H A Dport_proxy.cc51 auto req = std::make_shared<Request>( local
54 Packet pkt(req, MemCmd::ReadReq);
68 auto req = std::make_shared<Request>( local
71 Packet pkt(req, MemCmd::WriteReq);
/gem5/src/cpu/simple/
H A Datomic.cc338 AtomicSimpleCPU::genMemFragmentRequest(const RequestPtr& req, Addr frag_addr,
356 req->setVirt(0, frag_addr, frag_size, flags, dataMasterId(),
358 req->setByteEnable(std::vector<bool>(it_start, it_end));
363 req->setVirt(0, frag_addr, frag_size, flags, dataMasterId(),
365 req->setByteEnable(std::vector<bool>());
380 const RequestPtr &req = data_read_req;
387 req->taskId(taskId());
396 predicate = genMemFragmentRequest(req, frag_addr, size, flags,
401 fault = thread->dtb->translateAtomic(req, thread->getTC(),
407 !req
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H A Dtiming.cc264 const RequestPtr &req = pkt->req;
268 if (pkt->isRead() && pkt->req->isLLSC()) {
269 TheISA::handleLockedRead(thread, pkt->req);
271 if (req->isMmappedIpr()) {
288 TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res,
294 PacketPtr pkt = buildPacket(req, read);
297 if (req->getFlags().isSet(Request::NO_ACCESS)) {
306 if (req->isLLSC()) {
307 do_access = TheISA::handleLockedWrite(thread, req, dcachePor
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/gem5/src/arch/power/
H A Dtlb.cc148 TLB::checkCacheability(const RequestPtr &req)
151 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
154 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
282 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
285 if (req->getVaddr() & 0x3) {
286 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
287 req->getSize());
293 Fault fault = p->pTable->translate(req);
301 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
305 Fault fault = p->pTable->translate(req);
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H A Dtlb.hh162 static Fault checkCacheability(const RequestPtr &req);
163 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
164 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
166 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
168 const RequestPtr &req, ThreadContext *tc,
171 const RequestPtr &req,
/gem5/src/arch/x86/
H A Dtlb.hh109 Fault translateInt(const RequestPtr &req, ThreadContext *tc);
111 Fault translate(const RequestPtr &req, ThreadContext *tc,
126 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
128 const RequestPtr &req, ThreadContext *tc,
139 * @param req Request to updated in-place.
144 Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
/gem5/src/mem/cache/prefetch/
H A Dbase.cc60 : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
61 masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
62 secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
63 paddress(pkt->req->getPaddr()), cacheMiss(miss)
65 unsigned int req_size = pkt->req->getSize();
70 Addr offset = pkt->req->getPaddr() - pkt->getAddr();
129 bool fetch = pkt->req->isInstFetch();
133 if (pkt->req
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/gem5/src/arch/mips/
H A Dtlb.cc145 TLB::checkCacheability(const RequestPtr &req)
150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
152 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
285 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
292 Fault fault = p->pTable->translate(req);
300 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
307 Fault fault = p->pTable->translate(req);
315 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
318 return translateInst(req, tc);
320 return translateData(req, t
[all...]
/gem5/src/arch/alpha/
H A Dtlb.hh117 static Fault checkCacheability(const RequestPtr &req, bool itb = false);
140 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
141 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
145 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
147 const RequestPtr &req, ThreadContext *tc,
150 const RequestPtr &req, ThreadContext *tc,
/gem5/src/gpu-compute/
H A Dfetch_unit.cc148 RequestPtr req = std::make_shared<Request>( local
152 PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
171 DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
182 DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
210 assert(pkt->req->hasPaddr());
211 assert(pkt->req->hasSize());
215 pkt->req->getPaddr());
222 pkt = new Packet(oldPkt->req, oldPkt->cmd);
226 new TheGpuISA::RawMachInst[pkt->req->getSize() /
243 pkt->req
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H A Dgpu_dyn_inst.hh397 setRequestFlags(RequestPtr req, bool setMemOrder=true) argument
401 req->setMemSpaceConfigFlags(Request::PRIVATE_SEGMENT);
403 req->setMemSpaceConfigFlags(Request::SPILL_SEGMENT);
405 req->setMemSpaceConfigFlags(Request::GLOBAL_SEGMENT);
407 req->setMemSpaceConfigFlags(Request::READONLY_SEGMENT);
409 req->setMemSpaceConfigFlags(Request::GROUP_SEGMENT);
417 req->setMemSpaceConfigFlags(Request::SCOPE_VALID |
420 req->setMemSpaceConfigFlags(Request::SCOPE_VALID |
423 req->setMemSpaceConfigFlags(Request::SCOPE_VALID |
426 req
[all...]
/gem5/src/mem/ruby/system/
H A DVIPERCoalescer.cc100 if (pkt->req->isKernel()) {
104 if (pkt->req->isAcquire() && (m_outstanding_inv == 0)) {
108 if (pkt->req->isRelease()) {
109 insertKernel(pkt->req->contextId(), pkt);
115 } else if (pkt->req->isKernel() && pkt->req->isRelease()) {
118 insertKernel(pkt->req->contextId(), pkt);
134 } else if (pkt->req->isKernel() && pkt->req->isAcquire()) {
138 } else if (pkt->req
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/gem5/src/systemc/ext/tlm_core/1/req_rsp/channels/req_rsp_channels/
H A Dput_get_imp.hh97 tlm_master_imp(tlm_put_if<REQ> &req, tlm_get_peek_if<RSP> &rsp) : argument
98 tlm_put_get_imp<REQ, RSP>(req, rsp)
107 tlm_slave_imp(tlm_get_peek_if<REQ> &req, tlm_put_if<RSP> &rsp) : argument
108 tlm_put_get_imp<RSP, REQ>(rsp, req)
/gem5/src/cpu/testers/directedtest/
H A DInvalidateGenerator.cc63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId); local
72 pkt = new Packet(req, cmd);
77 pkt = new Packet(req, cmd);
/gem5/src/dev/arm/
H A Drv_ctrl.cc166 CfgCtrlReg req = pkt->getLE<uint32_t>(); local
167 if (!req.start) {
169 req);
173 auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK));
177 req.dcc, req.site, req.pos, req.func, req.dev);
184 if (req
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/gem5/src/cpu/testers/rubytest/
H A DCheck.cc110 RequestPtr req = std::make_shared<Request>(m_address, 0, flags, local
112 req->setContext(index);
114 PacketPtr pkt = new Packet(req, cmd);
123 pkt->senderState = new SenderState(m_address, req->getSize());
148 RequestPtr req = std::make_shared<Request>(m_address, CHECK_SIZE, flags, local
155 PacketPtr pkt = new Packet(req, cmd);
159 pkt->senderState = new SenderState(m_address, req->getSize());
181 RequestPtr req = std::make_shared<Request>( local
184 req->setContext(index);
194 PacketPtr pkt = new Packet(req, cm
245 RequestPtr req = std::make_shared<Request>(m_address, CHECK_SIZE, flags, local
[all...]

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