Searched refs:pkt (Results 51 - 75 of 375) sorted by relevance

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/gem5/src/mem/
H A Dnoncoherent_xbar.hh108 recvTimingReq(PacketPtr pkt) override
110 return xbar.recvTimingReq(pkt, id);
114 recvAtomic(PacketPtr pkt) override
116 return xbar.recvAtomicBackdoor(pkt, id);
120 recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
122 return xbar.recvAtomicBackdoor(pkt, id, &backdoor);
126 recvFunctional(PacketPtr pkt) override
128 xbar.recvFunctional(pkt, id);
160 recvTimingResp(PacketPtr pkt) override
162 return xbar.recvTimingResp(pkt, i
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H A Ddramsim2.cc155 DRAMSim2::recvAtomic(PacketPtr pkt) argument
157 access(pkt);
160 return pkt->cacheResponding() ? 0 : 50000;
164 DRAMSim2::recvFunctional(PacketPtr pkt) argument
166 pkt->pushLabel(name());
168 functionalAccess(pkt);
172 pkt->trySatisfyFunctional(*i);
174 pkt->popLabel();
178 DRAMSim2::recvTimingReq(PacketPtr pkt) argument
181 if (pkt
371 recvAtomic(PacketPtr pkt) argument
377 recvFunctional(PacketPtr pkt) argument
383 recvTimingReq(PacketPtr pkt) argument
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H A Dmem_checker_monitor.cc89 MemCheckerMonitor::recvFunctional(PacketPtr pkt) argument
91 Addr addr = pkt->getAddr();
92 unsigned size = pkt->getSize();
99 masterPort.sendFunctional(pkt);
107 MemCheckerMonitor::recvFunctionalSnoop(PacketPtr pkt) argument
109 Addr addr = pkt->getAddr();
110 unsigned size = pkt->getSize();
115 slavePort.sendFunctionalSnoop(pkt);
123 MemCheckerMonitor::recvAtomic(PacketPtr pkt) argument
129 MemCheckerMonitor::recvAtomicSnoop(PacketPtr pkt) argument
135 recvTimingReq(PacketPtr pkt) argument
227 recvTimingResp(PacketPtr pkt) argument
323 recvTimingSnoopReq(PacketPtr pkt) argument
329 recvTimingSnoopResp(PacketPtr pkt) argument
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H A Dsimple_mem.hh79 const PacketPtr pkt; member in class:SimpleMemory::DeferredPacket
81 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
94 Tick recvAtomic(PacketPtr pkt) override;
96 PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
97 void recvFunctional(PacketPtr pkt) override;
98 bool recvTimingReq(PacketPtr pkt) override;
188 Tick recvAtomic(PacketPtr pkt);
189 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor);
190 void recvFunctional(PacketPtr pkt);
191 bool recvTimingReq(PacketPtr pkt);
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H A Dcoherent_xbar.hh112 recvTimingReq(PacketPtr pkt) override
114 return xbar.recvTimingReq(pkt, id);
118 recvTimingSnoopResp(PacketPtr pkt) override
120 return xbar.recvTimingSnoopResp(pkt, id);
124 recvAtomic(PacketPtr pkt) override
126 return xbar.recvAtomicBackdoor(pkt, id);
130 recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
132 return xbar.recvAtomicBackdoor(pkt, id, &backdoor);
136 recvFunctional(PacketPtr pkt) override
138 xbar.recvFunctional(pkt, i
317 forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id) argument
349 forwardAtomic(PacketPtr pkt, PortID exclude_slave_port_id) argument
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H A Dpacket_queue.cc75 PacketQueue::checkConflict(const PacketPtr pkt, const int blk_size) const argument
80 if (p.pkt->matchBlockAddr(pkt, blk_size))
87 PacketQueue::trySatisfyFunctional(PacketPtr pkt) argument
89 pkt->pushLabel(label);
97 found = pkt->trySatisfyFunctional(i->pkt);
101 pkt->popLabel();
107 PacketQueue::schedSendTiming(PacketPtr pkt, Tick when) argument
110 __func__, pkt
246 sendTiming(PacketPtr pkt) argument
261 sendTiming(PacketPtr pkt) argument
275 sendTiming(PacketPtr pkt) argument
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/gem5/src/dev/x86/
H A Dintdev.hh77 recvAtomic(PacketPtr pkt) argument
79 panic_if(pkt->cmd != MemCmd::MessageReq,
81 name(), pkt->cmd.toString(), getPeer());
82 pkt->headerDelay = pkt->payloadDelay = 0;
83 return device->recvMessage(pkt);
108 recvTimingResp(PacketPtr pkt) override
110 return device->recvResponse(pkt);
119 PacketPtr pkt = buildIntRequest(id, message); local
121 schedTimingReq(pkt, curTic
152 recvResponse(PacketPtr pkt) argument
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H A Dspeaker.cc41 X86ISA::Speaker::read(PacketPtr pkt) argument
43 assert(pkt->getAddr() == pioAddr);
44 assert(pkt->getSize() == 1);
51 pkt->setLE((uint8_t)controlVal);
52 pkt->makeAtomicResponse();
57 X86ISA::Speaker::write(PacketPtr pkt) argument
59 assert(pkt->getAddr() == pioAddr);
60 assert(pkt->getSize() == 1);
61 SpeakerControl val = pkt->getLE<uint8_t>();
73 pkt
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H A Dcmos.cc48 X86ISA::Cmos::read(PacketPtr pkt) argument
50 assert(pkt->getSize() == 1);
51 switch(pkt->getAddr() - pioAddr)
54 pkt->setLE(address);
57 pkt->setLE(readRegister(address));
62 pkt->makeAtomicResponse();
67 X86ISA::Cmos::write(PacketPtr pkt) argument
69 assert(pkt->getSize() == 1);
70 switch(pkt->getAddr() - pioAddr)
73 address = pkt
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H A Di8237.cc37 X86ISA::I8237::read(PacketPtr pkt) argument
39 assert(pkt->getSize() == 1);
40 Addr offset = pkt->getAddr() - pioAddr;
67 pkt->makeAtomicResponse();
72 X86ISA::I8237::write(PacketPtr pkt) argument
74 assert(pkt->getSize() == 1);
75 Addr offset = pkt->getAddr() - pioAddr;
103 uint8_t command = pkt->getLE<uint8_t>();
125 pkt->makeAtomicResponse();
/gem5/src/arch/generic/
H A Dmmapped_ipr.cc42 handlePseudoInst(ThreadContext *xc, Packet *pkt) argument
44 const Addr offset(pkt->getAddr() & IPR_IN_CLASS_MASK);
51 if (pkt->isRead())
52 pkt->set(ret, TheISA::GuestByteOrder);
56 GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt) argument
58 Addr va(pkt->getAddr());
63 handlePseudoInst(xc, pkt);
73 GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt) argument
75 Addr va(pkt->getAddr());
80 handlePseudoInst(xc, pkt);
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/gem5/src/learning_gem5/part2/
H A Dsimple_cache.hh87 void sendPacket(PacketPtr pkt);
109 Tick recvAtomic(PacketPtr pkt) override
118 void recvFunctional(PacketPtr pkt) override;
128 bool recvTimingReq(PacketPtr pkt) override;
166 void sendPacket(PacketPtr pkt);
172 bool recvTimingResp(PacketPtr pkt) override;
200 bool handleRequest(PacketPtr pkt, int port_id);
210 bool handleResponse(PacketPtr pkt);
214 * This function assumes the pkt is already a response packet and forwards
220 void sendResponse(PacketPtr pkt);
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H A Dsimple_memobj.hh80 void sendPacket(PacketPtr pkt);
102 Tick recvAtomic(PacketPtr pkt) override
111 void recvFunctional(PacketPtr pkt) override;
121 bool recvTimingReq(PacketPtr pkt) override;
158 void sendPacket(PacketPtr pkt);
164 bool recvTimingResp(PacketPtr pkt) override;
190 bool handleRequest(PacketPtr pkt);
199 bool handleResponse(PacketPtr pkt);
207 void handleFunctional(PacketPtr pkt);
/gem5/src/dev/arm/
H A Dsmmu_v3_slaveifc.cc107 SMMUv3SlaveInterface::schedTimingResp(PacketPtr pkt) argument
109 slavePort->schedTimingResp(pkt, nextCycle());
113 SMMUv3SlaveInterface::schedAtsTimingResp(PacketPtr pkt) argument
115 atsSlavePort.schedTimingResp(pkt, nextCycle());
124 SMMUv3SlaveInterface::recvAtomic(PacketPtr pkt) argument
127 slavePort->getPeer(), pkt->getAddr(), pkt->getSize());
131 proc.beginTransaction(SMMUTranslRequest::fromPacket(pkt));
133 SMMUAction a = smmu->runProcessAtomic(&proc, pkt);
140 SMMUv3SlaveInterface::recvTimingReq(PacketPtr pkt) argument
172 atsSlaveRecvAtomic(PacketPtr pkt) argument
190 atsSlaveRecvTimingReq(PacketPtr pkt) argument
215 atsMasterRecvTimingResp(PacketPtr pkt) argument
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H A Drtc_pl031.cc61 PL031::read(PacketPtr pkt) argument
63 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
64 assert(pkt->getSize() == 4);
65 Addr daddr = pkt->getAddr() - pioAddr;
93 if (readId(pkt, ambaId, pioAddr)) {
95 data = pkt->getLE<uint32_t>();
102 switch(pkt->getSize()) {
104 pkt->setLE<uint8_t>(data);
107 pkt
123 write(PacketPtr pkt) argument
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H A Drv_ctrl.cc56 RealViewCtrl::read(PacketPtr pkt) argument
58 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
59 assert(pkt->getSize() == 4);
60 Addr daddr = pkt->getAddr() - pioAddr;
64 pkt->setLE(params()->proc_id0);
67 pkt->setLE(params()->proc_id1);
72 pkt->setLE((uint32_t)(clk));
77 pkt->setLE((uint32_t)(clk100));
80 pkt
132 write(PacketPtr pkt) argument
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H A Da9scu.hh69 * @param pkt The memory request.
72 virtual Tick read(PacketPtr pkt);
76 * @param pkt The memory request.
79 virtual Tick write(PacketPtr pkt);
H A Damba_fake.hh68 virtual Tick read(PacketPtr pkt);
69 virtual Tick write(PacketPtr pkt);
/gem5/src/dev/i2c/
H A Dbus.hh113 * specified by pkt.
115 * @param pkt memory request packet
117 void updateSignals(PacketPtr pkt);
122 * @param pkt memory request packet
123 * @return true if pkt indicates that scl transition from 0 to 1
125 bool isClockSet(PacketPtr pkt) const;
130 * @param pkt memory request packet
131 * @return true if pkt indicates a new transmission
133 bool isStart(PacketPtr pkt) const;
138 * @param pkt memor
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H A Dbus.cc71 I2CBus::read(PacketPtr pkt) argument
73 assert(pkt->getAddr() == pioAddr + SB_CONTROLS);
75 pkt->setRaw<uint8_t>((sda << 1) | scl);
76 pkt->makeAtomicResponse();
90 I2CBus::write(PacketPtr pkt) argument
92 assert(pkt->getAddr() == pioAddr + SB_CONTROLS ||
93 pkt->getAddr() == pioAddr + SB_CONTROLC);
95 updateSignals(pkt);
98 if (isStart(pkt)) {
113 if (isEnd(pkt)) {
173 updateSignals(PacketPtr pkt) argument
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/gem5/src/mem/cache/prefetch/
H A Dbase.cc59 BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss) argument
60 : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
61 masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
62 secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
63 paddress(pkt->req->getPaddr()), cacheMiss(miss)
65 unsigned int req_size = pkt
83 notify(const PacketPtr &pkt) argument
127 observeAccess(const PacketPtr &pkt, bool miss) const argument
203 probeNotify(const PacketPtr &pkt, bool miss) argument
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/gem5/src/gpu-compute/
H A Dfetch_unit.cc152 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); local
156 pkt->dataStatic(&fetchBlock);
160 pkt->senderState = new ComputeUnit::ITLBPort::SenderState(wavefront);
163 pkt->senderState =
166 false, pkt->senderState);
174 computeUnit->sqcTLBPort->retries.push_back(pkt);
175 } else if (!computeUnit->sqcTLBPort->sendTimingReq(pkt)) {
185 computeUnit->sqcTLBPort->retries.push_back(pkt);
190 pkt->senderState =
194 computeUnit->sqcTLBPort->sendFunctional(pkt);
208 fetch(PacketPtr pkt, Wavefront *wavefront) argument
256 processFetchReturn(PacketPtr pkt) argument
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/gem5/src/dev/virtio/
H A Dpci.cc68 PciVirtIO::read(PacketPtr pkt) argument
70 const unsigned M5_VAR_USED size(pkt->getSize());
73 if (!getBAR(pkt->getAddr(), bar, offset))
81 vio.readConfig(pkt, offset - OFF_VIO_DEVICE);
85 pkt->makeResponse();
91 pkt->setLE<uint32_t>(vio.deviceFeatures);
97 pkt->setLE<uint32_t>(vio.getGuestFeatures());
103 pkt->setLE<uint32_t>(vio.getQueueAddress());
109 pkt->setLE<uint16_t>(vio.getQueueSize());
115 pkt
149 write(PacketPtr pkt) argument
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/gem5/src/dev/alpha/
H A Dbackdoor.cc103 AlphaBackdoor::read(PacketPtr pkt) argument
111 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
113 Addr daddr = pkt->getAddr() - pioAddr;
115 pkt->makeAtomicResponse();
117 switch (pkt->getSize())
123 pkt->setLE(alphaAccess->last_offset);
126 pkt->setLE(alphaAccess->version);
129 pkt->setLE(alphaAccess->numCPUs);
132 pkt
201 write(PacketPtr pkt) argument
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/gem5/src/mem/ruby/slicc_interface/
H A DRubySlicc_Util.hh101 testAndRead(Addr addr, DataBlock& blk, Packet *pkt) argument
103 Addr pktLineAddr = makeLineAddress(pkt->getAddr());
107 uint8_t *data = pkt->getPtr<uint8_t>();
108 unsigned int size_in_bytes = pkt->getSize();
109 unsigned startByte = pkt->getAddr() - lineAddr;
127 testAndReadMask(Addr addr, DataBlock& blk, WriteMask& mask, Packet *pkt) argument
129 Addr pktLineAddr = makeLineAddress(pkt->getAddr());
133 uint8_t *data = pkt->getPtr<uint8_t>();
134 unsigned int size_in_bytes = pkt->getSize();
135 unsigned startByte = pkt
156 testAndWrite(Addr addr, DataBlock& blk, Packet *pkt) argument
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