Lines Matching refs:pkt
155 DRAMSim2::recvAtomic(PacketPtr pkt)
157 access(pkt);
160 return pkt->cacheResponding() ? 0 : 50000;
164 DRAMSim2::recvFunctional(PacketPtr pkt)
166 pkt->pushLabel(name());
168 functionalAccess(pkt);
172 pkt->trySatisfyFunctional(*i);
174 pkt->popLabel();
178 DRAMSim2::recvTimingReq(PacketPtr pkt)
181 if (pkt->cacheResponding()) {
182 pendingDelete.reset(pkt);
197 if (pkt->isRead()) {
199 outstandingReads[pkt->getAddr()].push(pkt);
206 } else if (pkt->isWrite()) {
208 outstandingWrites[pkt->getAddr()].push(pkt);
213 accessAndRespond(pkt);
217 accessAndRespond(pkt);
226 DPRINTF(DRAMSim2, "Enqueueing address %lld\n", pkt->getAddr());
231 wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
251 DRAMSim2::accessAndRespond(PacketPtr pkt)
253 DPRINTF(DRAMSim2, "Access for address %lld\n", pkt->getAddr());
255 bool needsResponse = pkt->needsResponse();
259 access(pkt);
264 assert(pkt->isResponse());
267 Tick time = curTick() + pkt->headerDelay + pkt->payloadDelay;
269 pkt->headerDelay = pkt->payloadDelay = 0;
272 pkt->getAddr());
275 responseQueue.push_back(pkt);
283 pendingDelete.reset(pkt);
300 PacketPtr pkt = p->second.front();
312 accessAndRespond(pkt);
371 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
373 return memory.recvAtomic(pkt);
377 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
379 memory.recvFunctional(pkt);
383 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
386 return memory.recvTimingReq(pkt);