Searched refs:pkt (Results 301 - 325 of 375) sorted by relevance

<<1112131415

/gem5/src/mem/cache/tags/
H A Dcompressed_tags.cc166 CompressedTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) argument
177 SectorTags::insertBlock(pkt, blk);
H A Dsector_tags.hh134 * @param pkt Packet holding the address to update
137 void insertBlock(const PacketPtr pkt, CacheBlk *blk) override;
/gem5/src/mem/ruby/network/
H A DNetwork.hh118 virtual bool functionalRead(Packet *pkt) argument
120 virtual uint32_t functionalWrite(Packet *pkt) argument
/gem5/src/dev/virtio/
H A Dblock.cc62 VirtIOBlock::readConfig(PacketPtr pkt, Addr cfgOffset) argument
67 readConfigBlob(pkt, cfgOffset, (uint8_t *)&cfg_out);
H A Dblock.hh75 void readConfig(PacketPtr pkt, Addr cfgOffset);
H A Dconsole.hh73 void readConfig(PacketPtr pkt, Addr cfgOffset);
/gem5/src/dev/x86/
H A Di8042.hh144 Tick read(PacketPtr pkt) override;
146 Tick write(PacketPtr pkt) override;
/gem5/ext/dnet/
H A Dicmp.h121 uint8_t icmp_ip __flexarr; /* IP hdr + 8 bytes of pkt */
132 uint8_t icmp_ip __flexarr; /* IP hdr + 8 bytes of pkt */
239 #define icmp_pack_hdr_quote(hdr, type, code, word, pkt, len) do { \
244 memmove(quote_pack_p->icmp_ip, pkt, len); \
256 #define icmp_pack_hdr_needfrag(hdr, type, code, mtu, pkt, len) do { \
262 memmove(frag_pack_p->icmp_ip, pkt, len); \
/gem5/src/mem/ruby/network/garnet2.0/
H A DRouter.cc279 Router::functionalWrite(Packet *pkt) argument
282 num_functional_writes += m_switch->functionalWrite(pkt);
285 num_functional_writes += m_input_unit[i]->functionalWrite(pkt);
289 num_functional_writes += m_output_unit[i]->functionalWrite(pkt);
H A DOutputUnit.hh97 uint32_t functionalWrite(Packet *pkt);
H A DVirtualChannel.hh90 uint32_t functionalWrite(Packet *pkt);
/gem5/src/arch/riscv/insts/
H A Dstatic_inst.hh94 completeAcc(PacketPtr pkt, ExecContext *xc,
/gem5/src/dev/net/
H A Dsinic.hh263 Tick read(PacketPtr pkt) override;
264 Tick write(PacketPtr pkt) override;
312 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } argument
H A Di8254xGBe.hh527 Tick read(PacketPtr pkt) override;
528 Tick write(PacketPtr pkt) override;
530 Tick writeConfig(PacketPtr pkt) override;
553 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); } argument
/gem5/src/mem/cache/prefetch/
H A Dbop.hh146 void notifyFill(const PacketPtr& pkt) override;
H A Dsbooe.hh149 void notifyFill(const PacketPtr& pkt) override;
/gem5/src/cpu/checker/
H A Dcpu.cc214 PacketPtr pkt = Packet::createRead(mem_req); local
216 pkt->dataStatic(data);
220 dcachePort->sendFunctional(pkt);
226 delete pkt;
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.hh62 virtual bool recvTimingResp(PacketPtr pkt);
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.cc177 RubyTester::CpuPort::recvTimingResp(PacketPtr pkt) argument
181 safe_cast<RubyTester::SenderState*>(pkt->senderState);
188 delete pkt->senderState;
189 delete pkt;
/gem5/src/cpu/
H A Dbase.hh78 bool doMonitor(PacketPtr pkt);
171 return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
641 bool mwait(ThreadID tid, PacketPtr pkt);
/gem5/src/mem/
H A Dxbar.cc96 BaseXBar::calcPacketTiming(PacketPtr pkt, Tick header_delay) argument
106 pkt->headerDelay += offset + header_delay;
114 panic_if(pkt->headerDelay > SimClock::Int::us,
117 if (pkt->hasData()) {
122 pkt->payloadDelay = std::max<Tick>(pkt->payloadDelay,
123 divCeil(pkt->getSize(), width) *
/gem5/src/dev/arm/
H A Dsmmu_v3_transl.cc49 SMMUTranslRequest::fromPacket(PacketPtr pkt, bool ats) argument
52 req.addr = pkt->getAddr();
53 req.size = pkt->getSize();
54 req.sid = pkt->req->streamId();
55 req.ssid = pkt->req->hasSubstreamId() ?
56 pkt->req->substreamId() : 0;
57 req.isWrite = pkt->isWrite();
60 req.pkt = pkt;
76 req.pkt
[all...]
H A Drv_ctrl.hh172 * @param pkt The memory request.
175 Tick read(PacketPtr pkt) override;
179 * @param pkt The memory request.
182 Tick write(PacketPtr pkt) override;
/gem5/src/cpu/kvm/
H A Dbase.cc180 BaseKvmCPU::KVMCpuPort::submitIO(PacketPtr pkt) argument
183 Tick delay = sendAtomic(pkt);
184 delete pkt;
187 if (pendingMMIOPkts.empty() && sendTimingReq(pkt)) {
190 pendingMMIOPkts.push(pkt);
198 BaseKvmCPU::KVMCpuPort::recvTimingResp(PacketPtr pkt) argument
202 delete pkt;
1135 PacketPtr pkt = new Packet(mmio_req, cmd); local
1136 pkt->dataStatic(data);
1143 TheISA::handleIprWrite(tc, pkt)
[all...]
/gem5/src/arch/sparc/
H A Dtlb.hh179 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
180 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);

Completed in 41 milliseconds

<<1112131415