Searched refs:panic (Results 376 - 392 of 392) sorted by relevance

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/gem5/src/arch/x86/
H A Dprocess.cc169 panic("KVM CPU model does not support 32 bit processes");
/gem5/configs/ruby/
H A DGPU_RfO.py433 panic("This script requires the GPU_RfO protocol to be built.")
H A DGPU_VIPER.py397 panic("This script requires the GPU_VIPER protocol to be built.")
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh896 panic("Is stalled should have been cleared by stalling load!\n");
H A Dinst_queue_impl.hh1438 panic("Dependency graph %i (%s) (flat: %i) not empty!",
H A Dlsq_impl.hh100 panic("Invalid LSQ sharing policy. Options are: Dynamic, "
H A Dcommit_impl.hh1209 panic("Thread sync instructions are not handled yet.\n");
H A Dcpu.cc205 panic("Workload Size too large. Increase the 'MaxThreads' "
H A Dfetch_impl.hh1593 panic("Branch Count Fetch policy unimplemented\n");
H A Diew_impl.hh1330 panic("Unexpected memory type!\n");
/gem5/src/mem/cache/
H A Dcache.cc868 panic("Illegal target->source enum %d\n", target.source);
H A Dbase.cc711 panic("Invalid size for conditional read/write\n");
/gem5/src/cpu/simple/
H A Dtiming.cc599 panic("AMO requests should not access across a cache line boundary\n");
/gem5/src/arch/arm/linux/
H A Dprocess.cc1697 panic("Attempt to execute an ANGEL_SWI system call (newlib-related)");
/gem5/src/arch/arm/
H A Dmiscregs.cc1151 panic("Invalid exception level");
1195 panic("Invalid exception level");
/gem5/src/python/m5/
H A Dparams.py579 panic("CheckedInt subclass %s must define either\n" \
/gem5/src/sim/
H A Dsyscall_emul.hh1620 panic("KVM CPU model is not supported for this ISA");

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