| /gem5/src/mem/cache/ |
| H A D | base.cc | 548 // access in timing mode
579 // Note that we don't invoke the prefetcher at all in atomic mode.
583 // to pollute the cache in atomic mode since there is no bandwidth
585 // mode, though, this is the place to do it... see timingAccess()
1727 // if the cache is in write coalescing mode or (additionally) in
1728 // no allocation mode, and we have a write packet with an MSHR
1730 // then reset the write mode
2505 // Forward the request if the system is in cache bypass mode.
2516 // The cache should be flushed if we are in cache bypass mode,
2637 if (mode !
[all...] |
| /gem5/ext/systemc/src/sysc/kernel/ |
| H A D | sc_simcontext.h | 84 extern void sc_set_stop_mode( sc_stop_mode mode );
742 - sc_stop mode
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| /gem5/src/mem/cache/prefetch/ |
| H A D | queued.cc | 78 // Prefetchers only operate in Timing mode
85 const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
84 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
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| /gem5/src/gpu-compute/ |
| H A D | wavefront.cc | 282 Wavefront::remap(uint32_t vgprIndex, uint32_t size, uint8_t mode) argument
289 // and SP VGPR name spaces in HSAIL mode are separate so we need to adjust
291 if (mode == 1 && size > 4) {
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| /gem5/src/cpu/o3/ |
| H A D | lsq_impl.hh | 774 ThreadContext* tc, BaseTLB::Mode mode)
807 ThreadContext* tc, BaseTLB::Mode mode)
773 finish(const Fault &fault, const RequestPtr &req, ThreadContext* tc, BaseTLB::Mode mode) argument
806 finish(const Fault &fault, const RequestPtr &req, ThreadContext* tc, BaseTLB::Mode mode) argument
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| H A D | cpu.cc | 112 /* It is mandatory that all SMT threads use the same renaming mode as
313 // SMT is not supported in FS mode yet.
872 // new_mode is the new vector renaming mode
873 auto new_mode = RenameMode<TheISA::ISA>::mode(pc);
1163 "'timing' mode.\n");
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| /gem5/src/sim/ |
| H A D | syscall_emul.hh | 804 int mode = p->getSyscallArg(tc, index); local
845 return drv->open(tc, mode, host_flags);
888 sim_fd = open(redir_path.c_str(), host_flags, mode);
1041 uint32_t mode = process->getSyscallArg(tc, index); local
1044 // XXX translate mode flags via OS::something???
1045 hostMode = mode;
1142 uint32_t mode = p->getSyscallArg(tc, index); local
1149 mode_t hostMode = mode;
2340 * emulation mode. Since signal handlers cannot be registered, all
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| /gem5/src/arch/arm/insts/ |
| H A D | macromem.cc | 245 int64_t imm, AddrMode mode,
249 bool post = (mode == AddrMd_PostIndex);
250 bool writeback = (mode != AddrMd_Offset);
242 PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, bool exclusive, bool acrel, int64_t imm, AddrMode mode, IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) argument
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| H A D | macromem.hh | 452 bool exclusive, bool acrel, int64_t imm, AddrMode mode,
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| /gem5/util/stats/ |
| H A D | db.py | 146 self.mode = 'sum';
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| /gem5/src/arch/x86/regs/ |
| H A D | misc.hh | 138 //Register to keep handy values like the CPU mode in.
329 // address. In 64 bit mode this can be different from the above,
580 Bitfield<0> mode; member in namespace:X86ISA
784 Bitfield<8> lme; // Long mode enable
785 Bitfield<10> lma; // Long mode active
804 Bitfield<16> usr; // User mode
805 Bitfield<17> os; // Operating-system mode
948 * TSS Descriptor (long mode - 128 bits)
980 * TSS Descriptor (long mode - 128 bits)
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| /gem5/src/cpu/minor/ |
| H A D | fetch1.cc | 241 ThreadContext *tc, BaseTLB::Mode mode)
240 finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode) argument
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| H A D | lsq.cc | 264 ThreadContext *tc, BaseTLB::Mode mode)
328 ThreadContext *tc, BaseTLB::Mode mode)
263 finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode) argument
327 finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode) argument
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| /gem5/src/arch/arm/ |
| H A D | process.cc | 131 cpsr.mode = MODE_EL0T;
290 //Whether to enable "secure mode" in the executable
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| H A D | miscregs_types.hh | 73 Bitfield<4, 0> mode; member in namespace:ArmISA
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| H A D | miscregs.cc | 995 switch (cpsr.mode) {
1031 switch (cpsr.mode) {
1168 // In syscall-emulation mode, this test is skipped and DCZVA is always
|