Searched refs:mask (Results 76 - 100 of 141) sorted by relevance

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/gem5/src/arch/x86/
H A Disa.cc111 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
193 regVal[miscReg] = val & mask(reg_width);
H A Dtlb.cc204 } else if ((IOPort & ~mask(2)) == 0xCFC) {
211 (IOPort & mask(2)));
331 vaddr &= mask(32);
408 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
/gem5/src/mem/cache/tags/
H A Dfa_lru.cc150 CachesMask mask = 0; local
155 mask = blk->inCachesMask;
161 *in_caches_mask = mask;
303 panic_if(blk->inCachesMask != in_caches_mask, "Expected cache mask "
350 // Get the mask of all caches, in which the block didn't fit
/gem5/src/cpu/minor/
H A Dfunc_unit.hh100 uint64_t mask; member in class:MinorFUTiming
106 /** If true, instructions matching this mask/match should *not* be
H A DMinorCPU.py78 mask = Param.UInt64(0, "mask for testing ExtMachInst") variable in class:MinorFUTiming
80 " (ext_mach_inst & mask) == match")
/gem5/src/dev/sparc/
H A Diob.hh97 bool mask; member in struct:Iob::IntCtl
/gem5/src/dev/x86/
H A Dpc.cc90 entry.mask = 1;
H A Di82094aa.cc55 entry.mask = 1;
190 if (entry.mask) {
/gem5/src/mem/cache/prefetch/
H A Dsignature_path.hh153 sig &= mask(signatureBits);
/gem5/src/arch/arm/
H A Dsystem.hh272 /** Returns the physical address mask */
275 return mask(physAddrRange());
331 /** Returns the physical address mask for the system of a specific thread
H A Disa.cc437 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
697 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); variable
698 val |= (mask ^ 0x7FFF) & 0xBFFF;
1029 mask(31, 13) | mask(11, 11) | mask(8, 6);
1036 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1639 RegVal mask =
1641 newVal = (newVal & ~mask) | (oldValu
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H A Dstage2_lookup.cc108 stage1Te.pfn = (pa | (ipa & mask(stage2Te->N))) >> stage1Te.N;
H A Ddecoder.cc137 "IT detected, cond = %#x, mask = %#x\n",
138 itBits.cond, itBits.mask);
/gem5/src/arch/sparc/
H A Dfaults.cc318 Addr pcMask = pstate.am ? mask(32) : mask(64);
399 Addr pcMask = pstate.am ? mask(32) : mask(64);
485 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
493 PC = (TBA & ~mask(15)) |
495 ((TT << 5) & mask(14));
/gem5/src/dev/arm/
H A Dpl011.cc233 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
284 Pl011::setInterrupts(uint16_t ints, uint16_t mask) argument
288 imsc = mask;
H A Dufs_device.cc683 sensecodelist[3] = status & 0xF; //mask to be sure + sensecode
1234 int mask = 0x01; local
1273 taskCommandTrack |= mask << count;
1278 task_info.mask = mask << count;
1302 transferTrack |= mask << count;
1321 transferstart_info.mask = mask << count;
1353 taskHandler(&taskInfo.front().destination, taskInfo.front().mask,
1368 transferStartInfo.front().mask,
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/gem5/src/arch/arm/insts/
H A Dvfp.hh216 void finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask = FpscrExcMask);
370 int64_t minVal = ~mask(width-1);
375 int64_t maxVal = mask(width-1);
382 finalVal = result & mask(width);
387 (isNeg ? mask(64-width+1) : 0);
400 finalVal = mask(width-1);
420 uint64_t result = ((uint64_t) val) & mask(width);
425 return mask(width);
/gem5/src/cpu/pred/
H A Dtournament.cc76 localPredictorMask = mask(localHistoryBits);
88 // Set up the global history mask
89 // this is equivalent to mask(log2(globalPredictorSize)
97 // this is equivalent to mask(log2(choicePredictorSize)
101 historyRegisterMask = mask(globalHistoryBits);
H A Dbi_mode.cc57 historyRegisterMask = mask(globalHistoryBits);
/gem5/ext/systemc/src/sysc/datatypes/misc/
H A Dsc_concatref.h220 uint64 mask; local
226 mask = (uint64)~0;
228 (result & ~(mask << m_len_r));
232 mask = (uint64)~0;
233 result = result & ~(mask << m_len);
/gem5/src/systemc/ext/dt/misc/
H A Dsc_concatref.hh232 uint64 mask; local
237 mask = (uint64)~0;
239 (result & ~(mask << m_len_r));
242 mask = (uint64)~0;
243 result = result & ~(mask << m_len);
/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_signed.cpp58 // Andy Goodrich: added mask to first word transferred when processing
146 sc_digit mask; // Mask for partial word sets. local
158 mask = ~(-1 << left_shift);
159 dst_p[dst_i] = ( dst_p[dst_i] & ~mask );
175 sc_digit mask; // Mask for partial word sets. local
202 mask = ~(-1 << left_shift);
203 dst_p[dst_i] = ( ( dst_p[dst_i] & mask ) |
217 mask = ~(-2 << high_i) & DIGIT_MASK;
218 dst_p[dst_i] = digit[src_i] & mask;
228 mask
387 uint64 mask = ~0; local
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/gem5/src/systemc/dt/int/
H A Dsc_signed.cc58 // Andy Goodrich: added mask to first word transferred when processing
163 sc_digit mask; // Mask for partial word sets. local
171 mask = ~(~0U << left_shift);
172 dst_p[dst_i] = (dst_p[dst_i] & ~mask);
190 sc_digit mask; // Mask for partial word sets. local
209 mask = ~(~0U << left_shift);
210 dst_p[dst_i] = ((dst_p[dst_i] & mask) |
219 mask = ~(~1U << high_i) & DIGIT_MASK;
220 dst_p[dst_i] = digit[src_i] & mask;
226 mask
346 uint64 mask = ~0; local
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/gem5/src/dev/pci/
H A Dhost.cc189 const Addr offset(addr & mask(confDeviceBits));
H A Dcopy_engine.cc394 (cr.descChainAddr & ~mask(32));
400 (cr.descChainAddr & mask(32));
414 (cr.completionAddr & ~mask(32));
419 (cr.completionAddr & mask(32));

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