15389Sgblack@eecs.umich.edu/* 25446Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35389Sgblack@eecs.umich.edu * All rights reserved. 45389Sgblack@eecs.umich.edu * 55389Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65389Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75389Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85389Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95389Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105389Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115389Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125389Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135389Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145389Sgblack@eecs.umich.edu * this software without specific prior written permission. 155389Sgblack@eecs.umich.edu * 165389Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175389Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185389Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195389Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205389Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215389Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225389Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235389Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245389Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255389Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265389Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275389Sgblack@eecs.umich.edu * 285389Sgblack@eecs.umich.edu * Authors: Gabe Black 295389Sgblack@eecs.umich.edu */ 305389Sgblack@eecs.umich.edu 315389Sgblack@eecs.umich.edu/** @file 325389Sgblack@eecs.umich.edu * Implementation of PC platform. 335389Sgblack@eecs.umich.edu */ 345389Sgblack@eecs.umich.edu 3511793Sbrandon.potter@amd.com#include "dev/x86/pc.hh" 3611793Sbrandon.potter@amd.com 375389Sgblack@eecs.umich.edu#include <deque> 385389Sgblack@eecs.umich.edu#include <string> 395389Sgblack@eecs.umich.edu#include <vector> 405389Sgblack@eecs.umich.edu 415654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 425389Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 436658Snate@binkert.org#include "config/the_isa.hh" 445389Sgblack@eecs.umich.edu#include "cpu/intr_control.hh" 455643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 465636Sgblack@eecs.umich.edu#include "dev/x86/i8254.hh" 475830Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 485637Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 495389Sgblack@eecs.umich.edu#include "sim/system.hh" 505389Sgblack@eecs.umich.edu 515389Sgblack@eecs.umich.eduusing namespace std; 525389Sgblack@eecs.umich.eduusing namespace TheISA; 535389Sgblack@eecs.umich.edu 545638Sgblack@eecs.umich.eduPc::Pc(const Params *p) 555389Sgblack@eecs.umich.edu : Platform(p), system(p->system) 565389Sgblack@eecs.umich.edu{ 575446Sgblack@eecs.umich.edu southBridge = NULL; 585389Sgblack@eecs.umich.edu} 595389Sgblack@eecs.umich.edu 605446Sgblack@eecs.umich.eduvoid 615638Sgblack@eecs.umich.eduPc::init() 625446Sgblack@eecs.umich.edu{ 635446Sgblack@eecs.umich.edu assert(southBridge); 645643Sgblack@eecs.umich.edu 655643Sgblack@eecs.umich.edu /* 665643Sgblack@eecs.umich.edu * Initialize the timer. 675643Sgblack@eecs.umich.edu */ 685636Sgblack@eecs.umich.edu I8254 & timer = *southBridge->pit; 695446Sgblack@eecs.umich.edu //Timer 0, mode 2, no bcd, 16 bit count 705446Sgblack@eecs.umich.edu timer.writeControl(0x34); 715446Sgblack@eecs.umich.edu //Timer 0, latch command 725446Sgblack@eecs.umich.edu timer.writeControl(0x00); 735446Sgblack@eecs.umich.edu //Write a 16 bit count of 0 745635Sgblack@eecs.umich.edu timer.writeCounter(0, 0); 755635Sgblack@eecs.umich.edu timer.writeCounter(0, 0); 765643Sgblack@eecs.umich.edu 775643Sgblack@eecs.umich.edu /* 785643Sgblack@eecs.umich.edu * Initialize the I/O APIC. 795643Sgblack@eecs.umich.edu */ 805643Sgblack@eecs.umich.edu I82094AA & ioApic = *southBridge->ioApic; 815643Sgblack@eecs.umich.edu I82094AA::RedirTableEntry entry = 0; 825654Sgblack@eecs.umich.edu entry.deliveryMode = DeliveryMode::ExtInt; 835643Sgblack@eecs.umich.edu entry.vector = 0x20; 845643Sgblack@eecs.umich.edu ioApic.writeReg(0x10, entry.bottomDW); 855643Sgblack@eecs.umich.edu ioApic.writeReg(0x11, entry.topDW); 865829Sgblack@eecs.umich.edu entry.deliveryMode = DeliveryMode::Fixed; 875829Sgblack@eecs.umich.edu entry.vector = 0x24; 885829Sgblack@eecs.umich.edu ioApic.writeReg(0x18, entry.bottomDW); 895829Sgblack@eecs.umich.edu ioApic.writeReg(0x19, entry.topDW); 905829Sgblack@eecs.umich.edu entry.mask = 1; 915829Sgblack@eecs.umich.edu entry.vector = 0x21; 925829Sgblack@eecs.umich.edu ioApic.writeReg(0x12, entry.bottomDW); 935829Sgblack@eecs.umich.edu ioApic.writeReg(0x13, entry.topDW); 945829Sgblack@eecs.umich.edu entry.vector = 0x20; 955829Sgblack@eecs.umich.edu ioApic.writeReg(0x14, entry.bottomDW); 965829Sgblack@eecs.umich.edu ioApic.writeReg(0x15, entry.topDW); 975829Sgblack@eecs.umich.edu entry.vector = 0x28; 985829Sgblack@eecs.umich.edu ioApic.writeReg(0x20, entry.bottomDW); 995829Sgblack@eecs.umich.edu ioApic.writeReg(0x21, entry.topDW); 1005829Sgblack@eecs.umich.edu entry.vector = 0x2C; 1015829Sgblack@eecs.umich.edu ioApic.writeReg(0x28, entry.bottomDW); 1025829Sgblack@eecs.umich.edu ioApic.writeReg(0x29, entry.topDW); 1035843Sgblack@eecs.umich.edu entry.vector = 0x2E; 1045843Sgblack@eecs.umich.edu ioApic.writeReg(0x2C, entry.bottomDW); 1055843Sgblack@eecs.umich.edu ioApic.writeReg(0x2D, entry.topDW); 1065843Sgblack@eecs.umich.edu entry.vector = 0x30; 1075843Sgblack@eecs.umich.edu ioApic.writeReg(0x30, entry.bottomDW); 1085843Sgblack@eecs.umich.edu ioApic.writeReg(0x31, entry.topDW); 1096073Sgblack@eecs.umich.edu 1106073Sgblack@eecs.umich.edu /* 1116073Sgblack@eecs.umich.edu * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared 1126073Sgblack@eecs.umich.edu * these out and masked them before passing control to the OS. 1136073Sgblack@eecs.umich.edu */ 1146073Sgblack@eecs.umich.edu southBridge->pic1->maskAll(); 1156073Sgblack@eecs.umich.edu southBridge->pic2->maskAll(); 1165446Sgblack@eecs.umich.edu} 1175446Sgblack@eecs.umich.edu 1185389Sgblack@eecs.umich.eduvoid 1195638Sgblack@eecs.umich.eduPc::postConsoleInt() 1205389Sgblack@eecs.umich.edu{ 1215830Sgblack@eecs.umich.edu southBridge->ioApic->signalInterrupt(4); 1225830Sgblack@eecs.umich.edu southBridge->pic1->signalInterrupt(4); 1235389Sgblack@eecs.umich.edu} 1245389Sgblack@eecs.umich.edu 1255389Sgblack@eecs.umich.eduvoid 1265638Sgblack@eecs.umich.eduPc::clearConsoleInt() 1275389Sgblack@eecs.umich.edu{ 1285389Sgblack@eecs.umich.edu warn_once("Don't know what interrupt to clear for console.\n"); 1295389Sgblack@eecs.umich.edu //panic("Need implementation\n"); 1305389Sgblack@eecs.umich.edu} 1315389Sgblack@eecs.umich.edu 1325389Sgblack@eecs.umich.eduvoid 1335638Sgblack@eecs.umich.eduPc::postPciInt(int line) 1345389Sgblack@eecs.umich.edu{ 1355842Sgblack@eecs.umich.edu southBridge->ioApic->signalInterrupt(line); 1365389Sgblack@eecs.umich.edu} 1375389Sgblack@eecs.umich.edu 1385389Sgblack@eecs.umich.eduvoid 1395638Sgblack@eecs.umich.eduPc::clearPciInt(int line) 1405389Sgblack@eecs.umich.edu{ 1415842Sgblack@eecs.umich.edu warn_once("Tried to clear PCI interrupt %d\n", line); 1425389Sgblack@eecs.umich.edu} 1435389Sgblack@eecs.umich.edu 1445638Sgblack@eecs.umich.eduPc * 1455638Sgblack@eecs.umich.eduPcParams::create() 1465389Sgblack@eecs.umich.edu{ 1475638Sgblack@eecs.umich.edu return new Pc(this); 1485389Sgblack@eecs.umich.edu} 149