| /gem5/src/cpu/simple/ |
| H A D | base.hh | 106 TheISA::MachInst inst; member in class:BaseSimpleCPU
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| H A D | base.cc | 92 inst(),
506 inst = gtoh(inst);
524 decoder->moreBytes(pcState, fetchPC, inst);
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| H A D | atomic.cc | 698 ifetch_pkt.dataStatic(&inst);
705 // into the CPU object's inst field.
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| H A D | timing.cc | 704 ifetch_pkt->dataStatic(&inst);
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| /gem5/src/cpu/o3/ |
| H A D | rename.hh | 258 inline void renameSrcRegs(const DynInstPtr &inst, ThreadID tid);
261 inline void renameDestRegs(const DynInstPtr &inst, ThreadID tid);
492 /** Stat for total number of cycles spent stalling for a serializing inst. */
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| H A D | commit.hh | 477 void updateComInstStats(const DynInstPtr &inst);
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| H A D | fetch.hh | 306 bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc);
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| /gem5/src/arch/arm/ |
| H A D | utility.hh | 337 advancePC(PCState &pc, const StaticInstPtr &inst) argument
339 inst->advancePC(pc);
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| /gem5/src/cpu/pred/ |
| H A D | multiperspective_perceptron_tage.hh | 79 const StaticInstPtr &inst, Addr target) override;
230 const StaticInstPtr & inst,
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| H A D | statistical_corrector.cc | 289 const StaticInstPtr &inst, bool taken, BranchInfo * tage_bi,
292 int brtype = inst->isDirectCtrl() ? 0 : 2;
293 if (! inst->isUncondCtrl()) {
288 scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken, BranchInfo * tage_bi, Addr corrTarget) argument
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| H A D | bi_mode.cc | 155 bool squashed, const StaticInstPtr & inst, Addr corrTarget)
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| H A D | tournament.cc | 255 const StaticInstPtr & inst, Addr corrTarget)
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| H A D | tage_base.hh | 293 const StaticInstPtr & inst = StaticInst::nullStaticInstPtr,
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| H A D | statistical_corrector.hh | 256 Addr branch_pc, const StaticInstPtr &inst , bool taken,
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| H A D | multiperspective_perceptron.cc | 611 const StaticInstPtr & inst,
609 update(ThreadID tid, Addr instPC, bool taken, void *bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument
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| H A D | multiperspective_perceptron.hh | 1031 const StaticInstPtr & inst,
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| H A D | tage_base.cc | 585 const StaticInstPtr &inst, Addr target)
583 updateHistories(ThreadID tid, Addr branch_pc, bool taken, BranchInfo* bi, bool speculative, const StaticInstPtr &inst, Addr target) argument
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| /gem5/util/minorview/ |
| H A D | view.py | 371 lines = list(inst.table_line() for inst in insts)
415 inst = insts[i]
418 id_size, inst.id.to_striped_block(self.view.dataSelect))
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| /gem5/ext/pybind11/include/pybind11/detail/ |
| H A D | class.h | 260 auto inst = reinterpret_cast<instance *>(self); local
262 inst->allocate_layout();
264 inst->owned = true;
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| /gem5/src/cpu/ |
| H A D | base.hh | 500 * @param inst Instruction that just committed
503 virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
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| /gem5/ext/pybind11/include/pybind11/ |
| H A D | pybind11.h | 443 if (!self_value_and_holder.type || !self_value_and_holder.inst) {
1296 static void init_holder(detail::instance *inst, detail::value_and_holder &v_h, argument
1307 if (!v_h.holder_constructed() && inst->owned) {
1324 static void init_holder(detail::instance *inst, detail::value_and_holder &v_h, argument
1329 } else if (inst->owned || detail::always_construct_holder<holder_type>::value) {
1339 static void init_instance(detail::instance *inst, const void *holder_ptr) { argument
1340 auto v_h = inst->get_value_and_holder(detail::get_type_info(typeid(type)));
1342 register_instance(inst, v_h.value_ptr(), v_h.type);
1345 init_holder(inst, v_h, (const holder_type *) holder_ptr, v_h.value_ptr<type>());
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| /gem5/configs/common/ |
| H A D | Simulation.py | 142 inst = options.checkpoint_restore
147 inst += int(testsys.cpu[0].workload[0].simpoint)
149 checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst))
217 print("Creating checkpoint at inst:%d" % (checkpoint_inst))
342 # Sort SimPoints by starting inst count
382 print("Checkpoint #%d written. start inst:%d weight:%f" %
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_parser.cc | 708 TarmacParserRecord::printMismatchHeader(inst, pc);
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