/gem5/src/dev/net/ |
H A D | i8254xGBe.cc | 913 // If we're draining delay issuing this DMA 994 // If we're draining delay issuing this DMA 1462 if (igbe->regs.rdtr.delay()) { 1463 Tick delay = igbe->regs.rdtr.delay() * igbe->intClock(); local 1464 DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay); 1465 igbe->reschedule(igbe->rdtrEvent, curTick() + delay); 1469 Tick delay = igbe->regs.radv.idv() * igbe->intClock(); local 1470 DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay); 1472 igbe->schedule(igbe->radvEvent, curTick() + delay); 1914 Tick delay = igbe->regs.tidv.idv() * igbe->intClock(); local 1920 Tick delay = igbe->regs.tadv.idv() * igbe->intClock(); local [all...] |
H A D | i8254xGBe_defs.hh | 583 ADD_FIELD32(delay,0,16); // receive delay timer 601 ADD_FIELD32(idv,0,16); // absolute interrupt delay 646 ADD_FIELD32(idv,0,16); // interrupt delay 667 ADD_FIELD32(idv,0,16); // absolute interrupt delay
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/gem5/src/mem/cache/ |
H A D | base.cc | 223 // into account the delay of the xbar, if any, and just 284 // delay of the xbar. 339 // the delay provided by the crossbar 408 // all header delay should be paid for by the crossbar, unless 411 "%s saw a non-zero packet delay\n", name()); 981 BaseCache::calculateTagOnlyLatency(const uint32_t delay, argument 986 return ticksToCycles(delay) + lookup_lat; 990 BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, argument 1000 lat = ticksToCycles(delay) + lookup_lat + dataLatency; 1002 lat = ticksToCycles(delay) [all...] |
H A D | base.hh | 432 * @param delay The delay until the packet's metadata is present. 436 Cycles calculateTagOnlyLatency(const uint32_t delay, 443 * @param delay The delay until the packet's metadata is present. 447 Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, 1097 // the operation's latency is added to the payload delay. Consume 1098 // that payload delay here, meaning that the data is always stored 1320 * Access whether we need to delay the current write. 1325 bool delay(Add function in class:WriteAllocator [all...] |
H A D | mshr.hh | 512 * Adds a delay relative to the current tick to the current MSHR 513 * @param delay_ticks the desired delay in ticks 515 void delay(Tick delay_ticks) function
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/gem5/configs/example/ |
H A D | fs.py | 190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 284 drive_sys.iobridge = Bridge(delay='50ns',
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/gem5/ext/mcpat/cacti/ |
H A D | mat.cc | 481 // delay calculation for tags of fully associative cache 502 delay_bl_restore = bl_precharge_eq_drv->delay + 514 delay_subarray_out_drv_htree = delay_subarray_out_drv + subarray_out_wire->delay; 555 delay_bl_restore = bl_precharge_eq_drv->delay + 2.3 * (R_bl_precharge * C_bl + R_bl * C_bl / 2); 557 delay_bl_restore = bl_precharge_eq_drv->delay + 584 delay_subarray_out_drv_htree = delay_subarray_out_drv + subarray_out_wire->delay; 591 delay_wl_reset = MAX(r_predec->blk1->delay, r_predec->blk2->delay); 793 delay_cam_sl_restore = sl_precharge_eq_drv->delay 798 //matchline ops delay [all...] |
/gem5/src/mem/qos/ |
H A D | mem_ctrl.hh | 177 * @param delay response delay 180 Addr addr, uint64_t entries, double delay);
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/gem5/src/cpu/o3/ |
H A D | lsq_impl.hh | 1133 Cycles delay(0); 1140 if (d > delay) 1141 delay = d; 1145 return delay;
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H A D | lsq_unit.hh | 672 Cycles delay = req->handleIprRead(thread, main_pkt); local 675 cpu->schedule(wb, cpu->clockEdge(delay));
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/gem5/src/cpu/simple/ |
H A D | timing.cc | 272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 273 new IprEvent(pkt, this, clockEdge(delay)); 482 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 483 new IprEvent(dcache_pkt, this, clockEdge(delay)); 857 // delay processing of returned data until next CPU clock edge 990 // same tick, delay the second one
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/gem5/src/arch/mips/ |
H A D | isa.cc | 519 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) argument 528 cpu->schedule(cp0_event, cpu->clockEdge(delay));
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/gem5/src/cpu/kvm/ |
H A D | x86_cpu.cc | 1310 Tick delay(0); 1359 delay += dataPort.submitIO(pkt); 1364 return delay;
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/gem5/configs/common/ |
H A D | HMC.py | 342 delay=opt.total_ctrl_latency) for i in
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/gem5/src/dev/arm/ |
H A D | gic_v3_its.hh | 66 Tick delay; member in struct:ItsAction
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H A D | smmu_v3_transl.cc | 259 doDelay(yield, smmu.ifcSmmuLat - Cycles(1)); // remaining pipeline delay 301 doDelay(yield, smmu.smmuIfcLat - Cycles(1)); // remaining pipeline delay 1265 a.delay = 0; 1279 a.delay = 0; 1293 a.delay = 0;
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/gem5/ext/dsent/model/ |
H A D | ElectricalModel.cc | 478 "[Error] " + getInstanceName() + " -> Redeclaration of delay " + name_); 480 ElectricalDelay* delay = new ElectricalDelay(name_, this); local 481 m_delays_->set(name_, delay);
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/gem5/src/dev/storage/ |
H A D | ide_disk.cc | 70 : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay), 388 /** @todo we need to figure out what the delay actually will be */ 495 /** @todo we need to figure out what the delay actually will be */ 683 /** @todo make this a scheduled event to simulate disk delay */ 924 disk delay */ 1000 disk delay */
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