Searched refs:delay (Results 126 - 143 of 143) sorted by relevance

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/gem5/src/dev/net/
H A Di8254xGBe.cc913 // If we're draining delay issuing this DMA
994 // If we're draining delay issuing this DMA
1462 if (igbe->regs.rdtr.delay()) {
1463 Tick delay = igbe->regs.rdtr.delay() * igbe->intClock(); local
1464 DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay);
1465 igbe->reschedule(igbe->rdtrEvent, curTick() + delay);
1469 Tick delay = igbe->regs.radv.idv() * igbe->intClock(); local
1470 DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay);
1472 igbe->schedule(igbe->radvEvent, curTick() + delay);
1914 Tick delay = igbe->regs.tidv.idv() * igbe->intClock(); local
1920 Tick delay = igbe->regs.tadv.idv() * igbe->intClock(); local
[all...]
H A Di8254xGBe_defs.hh583 ADD_FIELD32(delay,0,16); // receive delay timer
601 ADD_FIELD32(idv,0,16); // absolute interrupt delay
646 ADD_FIELD32(idv,0,16); // interrupt delay
667 ADD_FIELD32(idv,0,16); // absolute interrupt delay
/gem5/src/mem/cache/
H A Dbase.cc223 // into account the delay of the xbar, if any, and just
284 // delay of the xbar.
339 // the delay provided by the crossbar
408 // all header delay should be paid for by the crossbar, unless
411 "%s saw a non-zero packet delay\n", name());
981 BaseCache::calculateTagOnlyLatency(const uint32_t delay, argument
986 return ticksToCycles(delay) + lookup_lat;
990 BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, argument
1000 lat = ticksToCycles(delay) + lookup_lat + dataLatency;
1002 lat = ticksToCycles(delay)
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H A Dbase.hh432 * @param delay The delay until the packet's metadata is present.
436 Cycles calculateTagOnlyLatency(const uint32_t delay,
443 * @param delay The delay until the packet's metadata is present.
447 Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
1097 // the operation's latency is added to the payload delay. Consume
1098 // that payload delay here, meaning that the data is always stored
1320 * Access whether we need to delay the current write.
1325 bool delay(Add function in class:WriteAllocator
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H A Dmshr.hh512 * Adds a delay relative to the current tick to the current MSHR
513 * @param delay_ticks the desired delay in ticks
515 void delay(Tick delay_ticks) function
/gem5/configs/example/
H A Dfs.py190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
284 drive_sys.iobridge = Bridge(delay='50ns',
/gem5/ext/mcpat/cacti/
H A Dmat.cc481 // delay calculation for tags of fully associative cache
502 delay_bl_restore = bl_precharge_eq_drv->delay +
514 delay_subarray_out_drv_htree = delay_subarray_out_drv + subarray_out_wire->delay;
555 delay_bl_restore = bl_precharge_eq_drv->delay + 2.3 * (R_bl_precharge * C_bl + R_bl * C_bl / 2);
557 delay_bl_restore = bl_precharge_eq_drv->delay +
584 delay_subarray_out_drv_htree = delay_subarray_out_drv + subarray_out_wire->delay;
591 delay_wl_reset = MAX(r_predec->blk1->delay, r_predec->blk2->delay);
793 delay_cam_sl_restore = sl_precharge_eq_drv->delay
798 //matchline ops delay
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/gem5/src/mem/qos/
H A Dmem_ctrl.hh177 * @param delay response delay
180 Addr addr, uint64_t entries, double delay);
/gem5/src/cpu/o3/
H A Dlsq_impl.hh1133 Cycles delay(0);
1140 if (d > delay)
1141 delay = d;
1145 return delay;
H A Dlsq_unit.hh672 Cycles delay = req->handleIprRead(thread, main_pkt); local
675 cpu->schedule(wb, cpu->clockEdge(delay));
/gem5/src/cpu/simple/
H A Dtiming.cc272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
273 new IprEvent(pkt, this, clockEdge(delay));
482 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
483 new IprEvent(dcache_pkt, this, clockEdge(delay));
857 // delay processing of returned data until next CPU clock edge
990 // same tick, delay the second one
/gem5/src/arch/mips/
H A Disa.cc519 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) argument
528 cpu->schedule(cp0_event, cpu->clockEdge(delay));
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc1310 Tick delay(0);
1359 delay += dataPort.submitIO(pkt);
1364 return delay;
/gem5/configs/common/
H A DHMC.py342 delay=opt.total_ctrl_latency) for i in
/gem5/src/dev/arm/
H A Dgic_v3_its.hh66 Tick delay; member in struct:ItsAction
H A Dsmmu_v3_transl.cc259 doDelay(yield, smmu.ifcSmmuLat - Cycles(1)); // remaining pipeline delay
301 doDelay(yield, smmu.smmuIfcLat - Cycles(1)); // remaining pipeline delay
1265 a.delay = 0;
1279 a.delay = 0;
1293 a.delay = 0;
/gem5/ext/dsent/model/
H A DElectricalModel.cc478 "[Error] " + getInstanceName() + " -> Redeclaration of delay " + name_);
480 ElectricalDelay* delay = new ElectricalDelay(name_, this); local
481 m_delays_->set(name_, delay);
/gem5/src/dev/storage/
H A Dide_disk.cc70 : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay),
388 /** @todo we need to figure out what the delay actually will be */
495 /** @todo we need to figure out what the delay actually will be */
683 /** @todo make this a scheduled event to simulate disk delay */
924 disk delay */
1000 disk delay */

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