Searched refs:ULL (Results 76 - 93 of 93) sorted by relevance

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/gem5/src/arch/arm/insts/
H A Dpred_inst.hh128 bigData |= (ULL(0xFF) << (i * 8));
/gem5/src/cpu/pred/
H A Dtage_sc_l_64KB.cc212 return (tag & ((ULL(1) << tagTableTagWidths[bank]) - 1));
H A Dtage_sc_l_8KB.cc185 & ((ULL(1) << tagTableTagWidths[bank]) - 1));
/gem5/src/sim/
H A Dpseudo_inst.cc502 return ULL(0);
/gem5/src/arch/arm/
H A Dutility.cc137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
H A Dsemihosting.cc580 const Addr phys_max = (1ULL << 32) - 1;
/gem5/src/arch/mips/
H A Ddsp.cc118 uint64_t ones = ~(0ULL);
131 return value += ULL(1) << (lsbpos - 1);
/gem5/src/arch/sparc/
H A Dtlb.cc367 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
1347 ptr |= ULL(1) << (13 + tsb_size);
H A Dfaults.cc585 tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
/gem5/src/gpu-compute/
H A Dcompute_unit.cc1004 gpuDynInst->statusBitVector &= (~(1ULL << index));
1010 gpuDynInst->statusBitVector &= (~(1ULL << index));
/gem5/src/dev/net/
H A Di8254xGBe_defs.hh247 inline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, ULL(1)); }
H A Di8254xGBe.cc2300 int ratio = (1ULL << (regs.rctl.rdmts() + 1));
/gem5/src/dev/storage/
H A Dide_disk.cc609 curPrdAddr = pciToDma((Addr)(prdTableBase & ~ULL(0x3)));
/gem5/src/arch/x86/
H A Dprocess.cc171 _gdtStart = ULL(0xffffd000);
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h66 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
/gem5/src/base/
H A Dcp_annotate.cc155 ~ULL(0x3FFF));
/gem5/src/systemc/dt/int/
H A Dsc_int_mask.cc52 # define UINT64_C(v) v ## ULL
/gem5/src/mem/
H A Ddram_ctrl.cc125 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());

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