/gem5/src/mem/ruby/system/ |
H A D | Sequencer.py | 36 abstract = True 51 support_data_reqs = Param.Bool(True, "data cache requests supported") 52 support_inst_reqs = Param.Bool(True, "inst cache requests supported") 53 is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
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/gem5/src/cpu/minor/ |
H A D | MinorCPU.py | 198 return True 202 return True 224 fetch2CycleInput = Param.Bool(True, 235 decodeCycleInput = Param.Bool(True, 241 executeCycleInput = Param.Bool(True, 275 executeSetTraceTimeOnCommit = Param.Bool(True, 280 executeAllowEarlyMemoryIssue = Param.Bool(True, 284 enableIdling = Param.Bool(True,
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/gem5/src/dev/sparc/ |
H A D | T1000.py | 73 ret_data64=0x0000000000000001, update_data=True) 77 ret_data64=0x0000000000000001, update_data=True) 81 ret_data64=0x0000000000000001, update_data=True) 85 ret_data64=0x0000000000000001, update_data=True) 89 ret_data64=0x0000000000000000, update_data=True) 93 ret_data64=0x0000000000000000, update_data=True) 97 ret_data64=0x0000000000000000, update_data=True) 101 ret_data64=0x0000000000000000, update_data=True)
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/gem5/src/systemc/tlm_bridge/ |
H A D | TlmBridge.py | 36 abstract = True 48 abstract = True
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/gem5/configs/common/cores/arm/ |
H A D | O3_ARM_v7a.py | 41 opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True), 43 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ] 160 is_read_only = True 162 writeback_clean = True 175 writeback_clean = True 188 is_read_only = True 190 writeback_clean = True 202 prefetch_on_access = True
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H A D | ex5_LITTLE.py | 107 writeback_clean = True 113 is_read_only = True 133 is_read_only = True 135 writeback_clean = True 147 prefetch_on_access = True
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H A D | ex5_big.py | 48 opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True), 50 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ] 158 writeback_clean = True 165 is_read_only = True 185 is_read_only = True 187 writeback_clean = True 199 prefetch_on_access = True
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/gem5/src/sim/ |
H A D | ClockDomain.py | 48 abstract = True
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H A D | ClockedObject.py | 62 abstract = True
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/gem5/src/dev/ps2/ |
H A D | PS2.py | 45 abstract = True
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/gem5/src/mem/cache/tags/indexing_policies/ |
H A D | IndexingPolicies.py | 35 abstract = True
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.py | 43 randomization flag is True)")
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/gem5/ext/googletest/googletest/test/ |
H A D | gtest_throw_on_failure_test.py | 71 """Runs a command; returns True/False if its exit code is/isn't 0.""" 92 should_fail: True iff the program is expected to fail. 141 should_fail=True) 151 should_fail=True) 161 should_fail=True) 167 should_fail=True)
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H A D | gtest_test_utils.py | 48 _SUBPROCESS_MODULE_AVAILABLE = True 95 _gtest_flags_are_parsed = True 142 shutil.rmtree(_temp_dir, ignore_errors=True) 208 def __init__(self, command, working_dir=None, capture_stderr=True, env=None): 223 terminated_by_signal True iff the child process has been terminated 226 exited True iff the child process exited normally. 247 cwd=working_dir, universal_newlines=True, env=env) 293 else: # os.WIFEXITED(ret_code) should return True here. 297 self.terminated_by_signal = True 302 self.exited = True [all...] |
/gem5/configs/example/ |
H A D | sc_main.py | 38 root = Root(full_system=True, systemc_kernel=kernel)
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | PyTrafficGen.py | 65 @cxxMethod(override=True)
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/gem5/src/systemc/tests/ |
H A D | config.py | 41 root = Root(full_system=True, systemc_kernel=kernel)
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/gem5/tests/configs/ |
H A D | rubytest-ruby.py | 67 check_flush = True 100 system.ruby.randomization = True 114 ruby_port.no_retry_on_stall = True 120 ruby_port.using_ruby_tester = True
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/gem5/src/dev/ |
H A D | Device.py | 51 abstract = True 77 abstract = True 84 abstract = True 124 ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
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/gem5/ext/pybind11/tests/ |
H A D | test_gil_scoped.py | 9 process.daemon = True 41 thread.daemon = True 64 assert _run_in_process(_python_to_cpp_to_python_from_threads, 8, parallel=True) == 0
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/gem5/src/cpu/pred/ |
H A D | BranchPredictor.py | 38 abstract = True 47 indirectHashGHR = Param.Bool(True, "Hash branch predictor GHR") 48 indirectHashTargets = Param.Bool(True, "Hash path history targets") 61 abstract = True 145 speculativeHistUpdate = Param.Bool(True, 201 optionalAgeReset = Param.Bool(True, 208 abstract = True 237 truncatePathHist = Param.Bool(True, 318 useHashing = True 319 useDirectionBit = True [all...] |
/gem5/src/arch/arm/ |
H A D | ArmSystem.py | 60 multi_proc = Param.Bool(True, "Multiprocessor system?") 68 "True if Security Extensions are implemented") 70 "True if Virtualization Extensions are implemented") 72 "True if Crypto Extensions is implemented") 73 have_lpae = Param.Bool(True, "True if LPAE is implemented") 79 "True if the register width of the highest implemented exception level " 84 "True if ASID is 16 bits in AArch64 (ARMv8)") 85 have_sve = Param.Bool(True, 86 "True i [all...] |
/gem5/util/pbs/ |
H A D | send.py | 115 doruns = True 118 update = True 122 docpts = True 124 clean = True 126 depend = True 128 onlyecho = True 130 force = True 137 listonly = True 143 runflag = True 147 verbose = True [all...] |
/gem5/ext/mcpat/regression/ |
H A D | regression.py | 65 test_passed = True 113 return True 116 valid_regression = True 122 power_region_file_found = True 190 found_test = True 214 found_test = True 226 found_test = True
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/gem5/util/batch/ |
H A D | send.py | 114 doruns = True 117 update = True 121 docpts = True 123 clean = True 125 depend = True 127 onlyecho = True 129 force = True 136 listonly = True 142 runflag = True 146 verbose = True [all...] |