Searched refs:RegVal (Results 26 - 50 of 83) sorted by relevance

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/gem5/src/arch/sparc/
H A Ddecoder.hh49 RegVal asi;
96 setContext(RegVal _asi)
H A Dprocess.cc186 argsInit(sizeof(RegVal), PageBytes);
438 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
439 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
440 RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
441 RegVal CWP = tc->readMiscReg(MISCREG_CWP);
442 RegVal origCWP = CWP;
450 RegVal sp = tc->readIntReg(StackPointerReg);
473 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
474 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
475 RegVal Otherwi
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H A Disa.hh119 void setFSReg(int miscReg, RegVal val, ThreadContext *tc);
120 RegVal readFSReg(int miscReg, ThreadContext * tc);
186 RegVal readMiscRegNoEffect(int miscReg) const;
187 RegVal readMiscReg(int miscReg, ThreadContext *tc);
189 void setMiscRegNoEffect(int miscReg, RegVal val);
190 void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
H A Dprocess.hh112 RegVal getSyscallArg(ThreadContext *tc, int &i);
116 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
156 RegVal getSyscallArg(ThreadContext *tc, int &i);
160 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
H A Dfaults.cc305 RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
306 RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
309 RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
310 RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
311 RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
312 RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
313 RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
384 RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
385 RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
388 RegVal CC
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/gem5/src/arch/alpha/
H A Disa.cc77 RegVal
97 RegVal
117 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
143 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
/gem5/src/cpu/o3/
H A Dregfile.hh79 std::vector<RegVal> intRegFile;
83 std::vector<RegVal> floatRegFile;
96 std::vector<RegVal> ccRegFile;
184 RegVal
194 RegVal
199 RegVal floatRegBits = floatRegFile[phys_reg->index()];
291 RegVal
305 setIntReg(PhysRegIdPtr phys_reg, RegVal val)
317 setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
366 setCCReg(PhysRegIdPtr phys_reg, RegVal va
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H A Dcpu.hh340 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
345 RegVal readMiscReg(int misc_reg, ThreadID tid);
348 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
353 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
355 RegVal readIntReg(PhysRegIdPtr phys_reg);
357 RegVal readFloatReg(PhysRegIdPtr phys_reg);
410 RegVal readCCReg(PhysRegIdPtr phys_reg);
412 void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
414 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
422 void setCCReg(PhysRegIdPtr phys_reg, RegVal va
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H A Ddyn_inst.hh111 std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
139 RegVal
149 setMiscReg(int misc_reg, RegVal val) override
173 RegVal
185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
270 RegVal
276 RegVal
377 RegVal
387 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
394 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal va
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H A Dthread_context_impl.hh207 RegVal
214 RegVal
257 RegVal
265 O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val)
274 O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val)
312 O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val)
346 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
355 O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val)
/gem5/src/arch/mips/
H A Disa.cc188 RegVal procIDMask = 0; // Read-Only register
202 RegVal cfg_Mask = 0x7FFF0007;
224 RegVal cfg1_Mask = 0; // Read Only Register
241 RegVal cfg2_Mask = 0x7000F000; // Read Only Register
257 RegVal cfg3_Mask = 0; // Read Only Register
267 RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
277 RegVal SC_Mask = 0x0000F3C0;
287 RegVal IC_Mask = 0x000003E0;
296 RegVal wh_Mask = 0x7FFF0FFF;
306 RegVal pc_Mas
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H A Dutility.hh77 RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
78 RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
/gem5/src/cpu/checker/
H A Dthread_context.hh238 RegVal
244 RegVal
340 RegVal
347 setIntReg(RegIndex reg_idx, RegVal val) override
354 setFloatReg(RegIndex reg_idx, RegVal val) override
382 setCCReg(RegIndex reg_idx, RegVal val) override
424 RegVal
430 RegVal
437 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
446 setMiscReg(RegIndex misc_reg, RegVal va
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H A Dcpu.hh191 RegVal
199 RegVal
325 RegVal
366 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
375 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
384 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
454 RegVal
460 RegVal
467 setMiscRegNoEffect(int misc_reg, RegVal val)
476 setMiscReg(int misc_reg, RegVal va
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/gem5/src/cpu/
H A Dsimple_thread.hh106 RegVal floatRegs[TheISA::NumFloatRegs];
107 RegVal intRegs[TheISA::NumIntRegs];
111 RegVal ccRegs[TheISA::NumCCRegs];
284 RegVal
295 RegVal
300 RegVal regVal(readFloatRegFlat(flatIndex));
441 RegVal
459 setIntReg(RegIndex reg_idx, RegVal val) override
469 setFloatReg(RegIndex reg_idx, RegVal val) override
512 setCCReg(RegIndex reg_idx, RegVal va
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/gem5/src/arch/arm/
H A Dpmu.hh124 void setMiscReg(int misc_reg, RegVal val) override;
131 RegVal readMiscReg(int misc_reg) override;
199 RegVal readMiscRegInt(int misc_reg);
287 void setOverflowStatus(RegVal new_val);
573 RegVal reg_pmcnten;
582 RegVal reg_pminten;
585 RegVal reg_pmovsr;
619 static const RegVal reg_pmcr_wr_mask;
/gem5/src/arch/riscv/
H A Dfaults.hh109 virtual RegVal trap_value() const { return 0; }
145 RegVal trap_value() const override { return _inst; }
209 RegVal trap_value() const override { return _addr; }
222 RegVal trap_value() const override { return pcState.pc(); }
H A Disa.cc98 RegVal
111 RegVal
169 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
180 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
/gem5/src/arch/x86/
H A Dpseudo_inst.cc55 RegVal rflags = tc->readMiscReg(MISCREG_RFLAGS);
H A Disa.cc110 memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
127 RegVal
138 RegVal
146 RegVal fsw = regVal[MISCREG_FSW];
147 RegVal top = regVal[MISCREG_X87_TOP];
155 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
197 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
199 RegVal newVal = val;
H A Dsystem.cc103 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (RegVal)attr);
176 tc->setMiscReg(MISCREG_CS, (RegVal)cs);
188 tc->setMiscReg(MISCREG_DS, (RegVal)ds);
189 tc->setMiscReg(MISCREG_ES, (RegVal)ds);
190 tc->setMiscReg(MISCREG_FS, (RegVal)ds);
191 tc->setMiscReg(MISCREG_GS, (RegVal)ds);
192 tc->setMiscReg(MISCREG_SS, (RegVal)ds);
207 tc->setMiscReg(MISCREG_TR, (RegVal)tss);
/gem5/src/sim/
H A Dsyscall_desc.cc51 RegVal arg[6] M5_VAR_USED;
H A Dprocess.hh76 virtual RegVal getSyscallArg(ThreadContext *tc, int &i) = 0;
77 virtual RegVal getSyscallArg(ThreadContext *tc, int &i, int width);
78 virtual void setSyscallArg(ThreadContext *tc, int i, RegVal val) = 0;
163 Process *new_p, RegVal flags);
/gem5/src/cpu/minor/
H A Dexec_context.hh143 RegVal
151 RegVal
200 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
208 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
355 RegVal
361 RegVal
368 setMiscReg(int misc_reg, RegVal val) override
373 RegVal
382 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
415 RegVal
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/gem5/src/cpu/simple/
H A Dexec_context.hh177 RegVal
188 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
198 RegVal
210 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
367 RegVal
377 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
385 RegVal
395 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
407 RegVal
419 setMiscReg(int misc_reg, RegVal va
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