Searched refs:ISA (Results 26 - 37 of 37) sorted by relevance
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| /gem5/src/arch/x86/ |
| H A D | decoder.hh | 51 class ISA;
238 Decoder(ISA* isa = nullptr) : basePC(0), origPC(0), offset(0),
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| /gem5/src/cpu/ |
| H A D | thread_context.hh | 60 class ISA;
85 * ExecContext provides ISA access to the CPU (meaning it is
89 * be implemented so that the ISA can access whatever state it needs.
143 virtual TheISA::ISA *getIsaPtr() = 0;
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| H A D | simple_thread.hh | 113 TheISA::ISA *const isa; // one "instance" of the current ISA.
139 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
144 TheISA::ISA *_isa);
206 TheISA::ISA *getIsaPtr() override { return isa; }
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| /gem5/src/arch/arm/ |
| H A D | decoder.cc | 57 Decoder::Decoder(ISA* isa)
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| H A D | utility.cc | 151 auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
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| H A D | miscregs.cc | 2847 ISA::initializeMiscRegMetadata()
2850 // ISA object, so there's no need to initialize them multiple times.
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| /gem5/src/arch/alpha/ |
| H A D | ev5.cc | 87 // Insure ISA semantics
111 ISA::readIpr(int idx, ThreadContext *tc)
220 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
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| /gem5/src/cpu/o3/ |
| H A D | thread_context_impl.hh | 188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
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| H A D | thread_context.hh | 89 TheISA::ISA *
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| H A D | cpu.cc | 114 vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
224 assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
873 auto new_mode = RenameMode<TheISA::ISA>::mode(pc);
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| H A D | cpu.hh | 85 //Stuff that's pretty ISA independent will go here.
605 std::vector<TheISA::ISA *> isa;
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| /gem5/src/cpu/checker/ |
| H A D | thread_context.hh | 127 TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
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