Searched hist:9921 (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/arch/x86/regs/ | ||
| H A D | ccr.hh | 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
| H A D | int.hh | diff 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
| /gem5/src/arch/x86/ | ||
| H A D | x86_traits.hh | diff 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
| H A D | registers.hh | diff 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
| H A D | utility.cc | diff 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
| /gem5/src/mem/slicc/ast/ | ||
| H A D | FuncCallExprAST.py | diff 12662:bcda9eb2aef5 Mon Apr 16 19:37:00 EDT 2018 John Alsop <johnathan.alsop@amd.com> mem-ruby: enable DPRINTFN calls in slicc for temporary debug printing Change-Id: Ib92f8bb4ab7b61ebc96b935cb8abc42cf5ec6ac8 Reviewed-on: https://gem5-review.googlesource.com/9921 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/x86/isa/ | ||
| H A D | operands.isa | diff 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
| /gem5/src/cpu/o3/ | ||
| H A D | O3CPU.py | diff 9921:ee049bfce978 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> arch/x86: add support for explicit CC register file Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch. |
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