Searched hist:4965 (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | Bridge.py | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| H A D | bridge.hh | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| H A D | bridge.cc | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| /gem5/configs/common/ | ||
| H A D | Caches.py | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| H A D | FSConfig.py | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| /gem5/src/dev/ | ||
| H A D | io_device.hh | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| /gem5/configs/example/ | ||
| H A D | fs.py | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
| /gem5/src/mem/cache/ | ||
| H A D | cache.hh | diff 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
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