Searched hist:2010 (Results 76 - 100 of 929) sorted by relevance

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/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/
H A Dextract.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/x87/load_constants/
H A D__init__.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/x87/
H A Dno_operation.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/x87/stack_management/
H A D__init__.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dclear_state.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dstack_control.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/
H A D__init__.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/
H A Doutputblock.isadiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/arm/insts/
H A Dbranch.hhdiff 7153:6ce0bf0ddaf3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Eliminate the old style branch instructions.
diff 7149:97666c2fc7a5 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement new base classes for branches.
diff 7144:097e00bcf084 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of the unused Jump format.
diff 7099:1949ba4db2cf Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.
H A Dmisc.hhdiff 7409:1ff897327905 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make undefined instructions obey predication.
diff 7332:2e611548bb5a Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a new RegImmOp base class.
diff 7331:0897d3ccea91 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a RegRegImmOp base class.
diff 7330:4f882b59745d Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Widen the immediate fields in the misc instruction classes.
diff 7306:548a5ee3dc5f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make a base class for instructions that use only an immediate.
diff 7261:5ed14bce7261 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Rename the RevOp base class to something more generic.
diff 7253:38b991b82859 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a register, immediate, immediate to register base for [su]bfx.
diff 7241:0a9f0db3e5d8 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class to support usada8.
diff 7238:f68fa944baee Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class for the sel instruction.
diff 7233:687fa9b9c2b5 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class for extend and add instructions.
/gem5/src/arch/arm/isa/formats/
H A Dbranch.isadiff 7613:62159049ca81 Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement DBG instruction that doesn't do much for now.
diff 7605:94b2f78894ca Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement DSB, DMB, ISB
diff 7603:66d853e566d2 Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement CLREX
diff 7602:cd1930acae4e Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: BX instruction can be contitional if last instruction in a IT block

Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
diff 7419:10e7f0f18461 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Hook the misc instructions into the thumb decoder.
diff 7344:82a4e24e7fad Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: BXJ should be BX when there is no J support
diff 7316:bb190cb8ee69 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the CPS instruction.
diff 7290:ea9189fbb84f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure some undefined thumb32 instructions fault.
diff 7284:cff2ad25550e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the enterx and leavex instructions.
diff 7281:e67b0c646268 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: When an instruction is intentionally undefined, fault on it.
H A Dmem.isadiff 7499:be7c22eb8c20 Thu Jul 15 05:11:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.
diff 7417:a573ee3adc96 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Treat LDRD in ARM with an odd index as an undefined instruction.
diff 7314:f254f66afb11 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the SRS instruction.
diff 7309:35b6ca04e5b9 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode TBB and TBH.
diff 7305:6ed0e7460ed5 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the arm version of ldrexd.
diff 7304:ce1844ce6412 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the strex instructions.
diff 7293:a907ebdb7ee9 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the RFE instruction.
diff 7290:ea9189fbb84f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure some undefined thumb32 instructions fault.
diff 7280:fe6d787ed4c9 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the thumb version of the ldrd and strd instructions.
diff 7279:157b02cc0ba1 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Explicitly keep track of the second destination for double loads/stores.
H A Dfp.isadiff 7643:775ccd204013 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Seperate out the renamable bits in the FPSCR.
diff 7639:8c09b7ff5b57 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement all ARM SIMD instructions.
diff 7591:aabe621e58df Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Decode neon memory instructions.
diff 7435:62bdb68bb314 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the neon instruction space.
diff 7413:18e0f95d1f32 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder.
diff 7407:70f65d4c7fe3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of some of the old FP implementation.
diff 7398:063002e7106b Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement conversion to/from half precision.
diff 7394:bd00fbc41bb1 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.
diff 7392:43b0cd94ced6 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the version of VMRS that writes to the APSR.
diff 7389:714dea5b5298 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the VCMPE instruction.
H A Dmisc.isadiff 7757:d7360f5052b2 Mon Nov 15 15:04:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.

Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
diff 7652:f2621206b062 Wed Aug 25 20:10:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: Adding a bogus fault that does nothing.
This fault can used to flush the pipe, not including the faulting instruction.

The particular case I needed this was for a self-modifying code. It needed to
drain the store queue and force the following instruction to refetch from
icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.
diff 7583:665d71561298 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Implement some more misc registers
diff 7420:498b27bc326d Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement a version of mcr and mrc that works in user mode.
diff 7404:bfc74724914e Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
diff 7391:475d53c618c7 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Ignore reads and writes to DCIMVAC.
diff 7358:69a04e7b14eb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move the CP15 decode block into a function.
diff 7355:8d9b757b3583 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Warn/ignore when TLB maintenance operations are performed.
diff 7351:d90afcb8724e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Convert the CP15 registers from MPU to MMU.
diff 7300:3b491ad98fea Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.
/gem5/src/arch/arm/isa/insts/
H A Dfp.isadiff 7783:9b880b40ac10 Tue Dec 07 19:19:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Make all instructions that write a misc. register not perform the write until commit.

ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes. Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
diff 7648:3e561a5c0456 Wed Aug 25 20:10:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
diff 7644:62873d5c2bfc Wed Aug 25 20:10:00 EDT 2010 Ali Saidi <ali.saidi@arm.com> ARM: Fix VFP enabled checks for mem instructions
diff 7643:775ccd204013 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Seperate out the renamable bits in the FPSCR.
diff 7640:5286a8a469c5 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
diff 7639:8c09b7ff5b57 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement all ARM SIMD instructions.
diff 7398:063002e7106b Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement conversion to/from half precision.
diff 7397:cbd950459a29 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Clean up VFP
diff 7396:53454ef35b46 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Clean up the implementation of the VFP instructions.
/gem5/src/arch/arm/isa/templates/
H A Dmisc.isadiff 7712:7733c562e5e3 Fri Oct 22 03:23:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA: Simplify various implementations of completeAcc.
diff 7705:fd65f85fcc0c Wed Oct 13 04:57:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Mem: Change the CLREX flag to CLEAR_LL.

CLREX is the name of an ARM instruction, not a name for this generic flag.
diff 7612:917946898102 Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> MEM: Make CLREX a first class request operation and clear locks in caches when it in received
diff 7609:70e5fb74b4fa Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement CLREX init/complete acc methods
diff 7332:2e611548bb5a Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a new RegImmOp base class.
diff 7331:0897d3ccea91 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a RegRegImmOp base class.
diff 7330:4f882b59745d Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Widen the immediate fields in the misc instruction classes.
diff 7306:548a5ee3dc5f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make a base class for instructions that use only an immediate.
diff 7261:5ed14bce7261 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Rename the RevOp base class to something more generic.
diff 7253:38b991b82859 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a register, immediate, immediate to register base for [su]bfx.
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractEntry.ccdiff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass
6882:898047a3672c Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
/gem5/src/mem/slicc/ast/
H A DOutPortDeclAST.pydiff 6999:f226c098c393 Wed Mar 10 19:22:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol
diff 6872:b26f60c254c1 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Added message type check to OutPortDeclAST.py

Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.
H A DExprAST.pydiff 6999:f226c098c393 Wed Mar 10 19:22:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol
/gem5/src/arch/arm/isa/
H A Dmain.isadiff 7119:5ad962dec52f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Define the load instructions from outside the decoder.
diff 7117:5d18ca349ca1 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Create a "decoder" directory for the files implementing the decoder.
/gem5/src/arch/x86/insts/
H A Dmicrofpop.ccdiff 7629:0f0c231e3e97 Mon Aug 23 19:14:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.
diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/mem/slicc/generate/
H A Dhtml.pydiff 7007:79413d1ec307 Fri Mar 12 21:42:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: Change the code generation so that the generated code is easier to read
/gem5/src/arch/x86/isa/formats/
H A Derror.isadiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/general_purpose/
H A D__init__.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dtest.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly

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