17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 313738Sciro.santilli@arm.com// Copyright (c) 2010-2013,2016,2018-2019 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu}; 647376Sgblack@eecs.umich.edu 657376Sgblack@eecs.umich.edutemplate <class VfpOp> 6612032Sandreas.sandberg@arm.comStaticInstPtr 677376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 687376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 697376Sgblack@eecs.umich.edu{ 707376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 717376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 727376Sgblack@eecs.umich.edu } else { 737376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 747376Sgblack@eecs.umich.edu } 757376Sgblack@eecs.umich.edu} 767376Sgblack@eecs.umich.edu 777376Sgblack@eecs.umich.edutemplate <class Micro> 787376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 797376Sgblack@eecs.umich.edu{ 807376Sgblack@eecs.umich.edu public: 817376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 827376Sgblack@eecs.umich.edu bool _wide) : 837376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 847376Sgblack@eecs.umich.edu { 857376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 867376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 877376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 887376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 897376Sgblack@eecs.umich.edu if (i == 0) 907376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 917376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 927376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 937376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 947376Sgblack@eecs.umich.edu nextIdxs(_dest); 957376Sgblack@eecs.umich.edu } 967376Sgblack@eecs.umich.edu } 977376Sgblack@eecs.umich.edu}; 987376Sgblack@eecs.umich.edu 997376Sgblack@eecs.umich.edutemplate <class VfpOp> 10012032Sandreas.sandberg@arm.comStaticInstPtr 1017376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1027376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1037376Sgblack@eecs.umich.edu{ 1047376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1057376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1067376Sgblack@eecs.umich.edu } else { 1077376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1087376Sgblack@eecs.umich.edu } 1097376Sgblack@eecs.umich.edu} 1107376Sgblack@eecs.umich.edu 1117376Sgblack@eecs.umich.edutemplate <class Micro> 1127376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1137376Sgblack@eecs.umich.edu{ 1147376Sgblack@eecs.umich.edu public: 1157376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1167376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1177376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1187376Sgblack@eecs.umich.edu { 1197376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1207376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1217376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1227376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1237376Sgblack@eecs.umich.edu if (i == 0) 1247376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1257376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1267376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1277376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1287376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1297376Sgblack@eecs.umich.edu } 1307376Sgblack@eecs.umich.edu } 1317376Sgblack@eecs.umich.edu}; 1327376Sgblack@eecs.umich.edu 1337376Sgblack@eecs.umich.edutemplate <class VfpOp> 13412032Sandreas.sandberg@arm.comStaticInstPtr 1357376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1367376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1377376Sgblack@eecs.umich.edu{ 1387376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1397376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1407376Sgblack@eecs.umich.edu } else { 1417376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1427376Sgblack@eecs.umich.edu } 1437376Sgblack@eecs.umich.edu} 1447376Sgblack@eecs.umich.edu 1457376Sgblack@eecs.umich.edutemplate <class Micro> 1467376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1477376Sgblack@eecs.umich.edu{ 1487376Sgblack@eecs.umich.edu public: 1497376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1507376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1517376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1527376Sgblack@eecs.umich.edu { 1537376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1547376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1557376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1567376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1577376Sgblack@eecs.umich.edu if (i == 0) 1587376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1597376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1607376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1617376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1627376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1637376Sgblack@eecs.umich.edu } 1647376Sgblack@eecs.umich.edu } 1657376Sgblack@eecs.umich.edu}; 1667376Sgblack@eecs.umich.edu 1677376Sgblack@eecs.umich.edutemplate <class VfpOp> 16812032Sandreas.sandberg@arm.comStaticInstPtr 1697376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1707376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1717376Sgblack@eecs.umich.edu{ 1727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1747376Sgblack@eecs.umich.edu } else { 1757376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1767376Sgblack@eecs.umich.edu } 1777376Sgblack@eecs.umich.edu} 1787376Sgblack@eecs.umich.edu}}; 1797376Sgblack@eecs.umich.edu 1807322Sgblack@eecs.umich.edulet {{ 1817322Sgblack@eecs.umich.edu 1827322Sgblack@eecs.umich.edu header_output = "" 1837322Sgblack@eecs.umich.edu decoder_output = "" 1847322Sgblack@eecs.umich.edu exec_output = "" 1857322Sgblack@eecs.umich.edu 18610037SARM gem5 Developers vmsrCode = vmsrEnabledCheckCode + ''' 18710037SARM gem5 Developers MiscDest = Op1; 18810037SARM gem5 Developers ''' 18910037SARM gem5 Developers 19010037SARM gem5 Developers vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", 19110037SARM gem5 Developers { "code": vmsrCode, 1927760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 1937760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 1947648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 19510037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmsrIop); 19610037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop); 1977322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 1987324Sgblack@eecs.umich.edu 1997644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2007643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2017643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2027643Sgblack@eecs.umich.edu ''' 2037643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2047643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2057760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2067783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2078070SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative", 2088070SAli.Saidi@ARM.com "IsSquashAfter"]) 2097643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2107643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2117643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2127643Sgblack@eecs.umich.edu 21310037SARM gem5 Developers vmrsCode = vmrsEnabledCheckCode + ''' 21410037SARM gem5 Developers CPSR cpsr = Cpsr; 21510037SARM gem5 Developers SCR scr = Scr; 21610037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 21710037SARM gem5 Developers HCR hcr = Hcr; 21810037SARM gem5 Developers bool hypTrap = false; 21912106SRekai.GonzalezAlberquilla@arm.com switch(xc->tcBase()->flattenRegId(RegId(MiscRegClass, op1)).index()) { 22010037SARM gem5 Developers case MISCREG_FPSID: 22110037SARM gem5 Developers hypTrap = hcr.tid0; 22210037SARM gem5 Developers break; 22310037SARM gem5 Developers case MISCREG_MVFR0: 22410037SARM gem5 Developers case MISCREG_MVFR1: 22510037SARM gem5 Developers hypTrap = hcr.tid3; 22610037SARM gem5 Developers break; 22710037SARM gem5 Developers } 22810037SARM gem5 Developers if (hypTrap) { 22910474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 23010037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS); 23110037SARM gem5 Developers } 23210037SARM gem5 Developers } 23310037SARM gem5 Developers Dest = MiscOp1; 23410037SARM gem5 Developers ''' 23510037SARM gem5 Developers 23610037SARM gem5 Developers vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", 23710037SARM gem5 Developers { "code": vmrsCode, 2387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2397783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2407783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 24110037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmrsIop); 24210037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop); 2437324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2447333Sgblack@eecs.umich.edu 2457643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2467644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2477643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2487760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2497783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2507783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2517643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2527643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2537643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2547643Sgblack@eecs.umich.edu 25511513Sandreas.sandberg@arm.com vmrsApsrFpscrCode = vfpEnabledCheckCode + ''' 2568303SAli.Saidi@ARM.com FPSCR fpscr = FpCondCodes; 2578303SAli.Saidi@ARM.com CondCodesNZ = (fpscr.n << 1) | fpscr.z; 2588303SAli.Saidi@ARM.com CondCodesC = fpscr.c; 2598303SAli.Saidi@ARM.com CondCodesV = fpscr.v; 2607643Sgblack@eecs.umich.edu ''' 2618303SAli.Saidi@ARM.com vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", 2627643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2648303SAli.Saidi@ARM.com "op_class": "SimdFloatMiscOp" }) 2658303SAli.Saidi@ARM.com header_output += BasicDeclare.subst(vmrsApsrFpscrIop); 2668303SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); 2677643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2687643Sgblack@eecs.umich.edu 2697640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2708588Sgblack@eecs.umich.edu FpDest_uw = bits(imm, 31, 0); 2717333Sgblack@eecs.umich.edu ''' 2727396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2737333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2747760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2757760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2767396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2777396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2787333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2797333Sgblack@eecs.umich.edu 2807640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2818588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2828588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2837333Sgblack@eecs.umich.edu ''' 2847396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2857333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2887396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2897396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2907333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2917333Sgblack@eecs.umich.edu 2927640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2938588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2948588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2958588Sgblack@eecs.umich.edu FpDestP2_uw = bits(imm, 31, 0); 2968588Sgblack@eecs.umich.edu FpDestP3_uw = bits(imm, 63, 32); 2977333Sgblack@eecs.umich.edu ''' 2987396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2997333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 3007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3027396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 3037396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 3057333Sgblack@eecs.umich.edu 3067640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 3078588Sgblack@eecs.umich.edu FpDest_uw = FpOp1_uw; 3087333Sgblack@eecs.umich.edu ''' 3097396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 3117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3137396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 3147396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 3157333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 3167333Sgblack@eecs.umich.edu 3177640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3188588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3198588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3207333Sgblack@eecs.umich.edu ''' 3217396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3227333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3257396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3267396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3287333Sgblack@eecs.umich.edu 3297640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3308588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3318588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3328588Sgblack@eecs.umich.edu FpDestP2_uw = FpOp1P2_uw; 3338588Sgblack@eecs.umich.edu FpDestP3_uw = FpOp1P3_uw; 3347333Sgblack@eecs.umich.edu ''' 3357396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3367333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3417333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3427333Sgblack@eecs.umich.edu 34310037SARM gem5 Developers vmovCoreRegBCode = simdEnabledCheckCode + ''' 3448588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 3457333Sgblack@eecs.umich.edu ''' 3467396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3477333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3487760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3497760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3507396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3517396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3527333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3537333Sgblack@eecs.umich.edu 35410037SARM gem5 Developers vmovCoreRegHCode = simdEnabledCheckCode + ''' 3558588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 3567333Sgblack@eecs.umich.edu ''' 3577396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3587333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3617396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3627396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3637333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3647333Sgblack@eecs.umich.edu 3657640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3668588Sgblack@eecs.umich.edu FpDest_uw = Op1_uw; 3677333Sgblack@eecs.umich.edu ''' 3687396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3697333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3707760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3717760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3727396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3737396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3757333Sgblack@eecs.umich.edu 3767640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3777639Sgblack@eecs.umich.edu assert(imm < 4); 3788588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8); 3797333Sgblack@eecs.umich.edu ''' 3807396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3817333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3847396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3857396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3867333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3877333Sgblack@eecs.umich.edu 3887640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3897639Sgblack@eecs.umich.edu assert(imm < 2); 3908588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16); 3917333Sgblack@eecs.umich.edu ''' 3927396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3937333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3967396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3977396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3997333Sgblack@eecs.umich.edu 4007640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 4017639Sgblack@eecs.umich.edu assert(imm < 4); 4028588Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8)); 4037333Sgblack@eecs.umich.edu ''' 4047396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 4057333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 4067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4087396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 4097396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 4107333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 4117333Sgblack@eecs.umich.edu 4127640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 4137639Sgblack@eecs.umich.edu assert(imm < 2); 4148588Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16)); 4157333Sgblack@eecs.umich.edu ''' 4167396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4177333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4207396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4217396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4227333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4237333Sgblack@eecs.umich.edu 4247640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4258588Sgblack@eecs.umich.edu Dest = FpOp1_uw; 4267333Sgblack@eecs.umich.edu ''' 4277396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4287333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4307760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4317396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4327396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4337333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4347333Sgblack@eecs.umich.edu 4357640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4368588Sgblack@eecs.umich.edu FpDestP0_uw = Op1_uw; 4378588Sgblack@eecs.umich.edu FpDestP1_uw = Op2_uw; 4387333Sgblack@eecs.umich.edu ''' 4397396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4407333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4417760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4427760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4437396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4447396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4457333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4467333Sgblack@eecs.umich.edu 4477640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4488588Sgblack@eecs.umich.edu Dest_uw = FpOp2P0_uw; 4498588Sgblack@eecs.umich.edu Op1_uw = FpOp2P1_uw; 4507333Sgblack@eecs.umich.edu ''' 4517396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4527333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4537760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4547760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4557396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4567396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4577333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4587381Sgblack@eecs.umich.edu}}; 4597381Sgblack@eecs.umich.edu 4607381Sgblack@eecs.umich.edulet {{ 4617381Sgblack@eecs.umich.edu 4627381Sgblack@eecs.umich.edu header_output = "" 4637381Sgblack@eecs.umich.edu decoder_output = "" 4647381Sgblack@eecs.umich.edu exec_output = "" 4657364Sgblack@eecs.umich.edu 4667783SGiacomo.Gabrielli@arm.com singleSimpleCode = vfpEnabledCheckCode + ''' 4678607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4687396Sgblack@eecs.umich.edu FpDest = %(op)s; 4697783SGiacomo.Gabrielli@arm.com ''' 4707783SGiacomo.Gabrielli@arm.com singleCode = singleSimpleCode + ''' 4717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4727364Sgblack@eecs.umich.edu ''' 47310037SARM gem5 Developers singleTernOp = vfpEnabledCheckCode + ''' 47410037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 47510037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 47610037SARM gem5 Developers float cOp1 = FpOp1; 47710037SARM gem5 Developers float cOp2 = FpOp2; 47810037SARM gem5 Developers float cOp3 = FpDestP0; 47910037SARM gem5 Developers FpDestP0 = ternaryOp(fpscr, %(palam)s, %(op)s, 48010037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 48110037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 48210037SARM gem5 Developers FpscrExc = fpscr; 48310037SARM gem5 Developers ''' 4847396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4857639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4867396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4877640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4888607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4897396Sgblack@eecs.umich.edu double dest = %(op)s; 4908588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 4918588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 4927783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4937396Sgblack@eecs.umich.edu ''' 49410037SARM gem5 Developers doubleTernOp = vfpEnabledCheckCode + ''' 49510037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 49610037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 49710037SARM gem5 Developers double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 49810037SARM gem5 Developers double cOp2 = dbl(FpOp2P0_uw, FpOp2P1_uw); 49910037SARM gem5 Developers double cOp3 = dbl(FpDestP0_uw, FpDestP1_uw); 50010037SARM gem5 Developers double cDest = ternaryOp(fpscr, %(palam)s, %(op)s, 50110037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 50210037SARM gem5 Developers FpDestP0_uw = dblLow(cDest); 50310037SARM gem5 Developers FpDestP1_uw = dblHi(cDest); 50410037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 50510037SARM gem5 Developers FpscrExc = fpscr; 50610037SARM gem5 Developers ''' 5077396Sgblack@eecs.umich.edu doubleBinOp = ''' 5088588Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 5098588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 5107639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 5117396Sgblack@eecs.umich.edu ''' 5127396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 5138588Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 5147396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 5157396Sgblack@eecs.umich.edu ''' 5167364Sgblack@eecs.umich.edu 51710037SARM gem5 Developers def buildTernaryFpOp(Name, base, opClass, singleOp, doubleOp, paramStr): 51810037SARM gem5 Developers global header_output, decoder_output, exec_output 51910037SARM gem5 Developers 52010037SARM gem5 Developers code = singleTernOp % { "op": singleOp, "palam": paramStr } 52110037SARM gem5 Developers sIop = InstObjParams(Name.lower() + "s", Name + "S", base, 52210037SARM gem5 Developers { "code": code, 52310037SARM gem5 Developers "predicate_test": predicateTest, 52410037SARM gem5 Developers "op_class": opClass }, []) 52510037SARM gem5 Developers code = doubleTernOp % { "op": doubleOp, "palam": paramStr } 52610037SARM gem5 Developers dIop = InstObjParams(Name.lower() + "d", Name + "D", base, 52710037SARM gem5 Developers { "code": code, 52810037SARM gem5 Developers "predicate_test": predicateTest, 52910037SARM gem5 Developers "op_class": opClass }, []) 53010037SARM gem5 Developers 53110037SARM gem5 Developers declareTempl = eval(base + "Declare"); 53210037SARM gem5 Developers constructorTempl = eval(base + "Constructor"); 53310037SARM gem5 Developers 53410037SARM gem5 Developers for iop in sIop, dIop: 53510037SARM gem5 Developers header_output += declareTempl.subst(iop) 53610037SARM gem5 Developers decoder_output += constructorTempl.subst(iop) 53710037SARM gem5 Developers exec_output += PredOpExecute.subst(iop) 53810037SARM gem5 Developers 53910037SARM gem5 Developers buildTernaryFpOp("Vfma", "FpRegRegRegOp", "SimdFloatMultAccOp", 54010037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, cOp3" ) 54110037SARM gem5 Developers buildTernaryFpOp("Vfms", "FpRegRegRegOp", "SimdFloatMultAccOp", 54210037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, cOp3" ) 54310037SARM gem5 Developers buildTernaryFpOp("Vfnma", "FpRegRegRegOp", "SimdFloatMultAccOp", 54410037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, -cOp3" ) 54510037SARM gem5 Developers buildTernaryFpOp("Vfnms", "FpRegRegRegOp", "SimdFloatMultAccOp", 54610037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, -cOp3" ) 54710037SARM gem5 Developers 5487760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 5497396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5507365Sgblack@eecs.umich.edu 5517396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 5527396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5537396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5547760SGiacomo.Gabrielli@arm.com { "code": code, 5557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5567760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5577396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 5587396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5597396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5607760SGiacomo.Gabrielli@arm.com { "code": code, 5617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5627760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5637365Sgblack@eecs.umich.edu 5647396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5657396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5667366Sgblack@eecs.umich.edu 5677396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5687396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5697396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5707396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5717366Sgblack@eecs.umich.edu 5727760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5737760SGiacomo.Gabrielli@arm.com "fpAddD") 5747760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5757760SGiacomo.Gabrielli@arm.com "fpSubD") 5767760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5777760SGiacomo.Gabrielli@arm.com "fpDivD") 5787760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5797760SGiacomo.Gabrielli@arm.com "fpMulD") 5807367Sgblack@eecs.umich.edu 58113979Sciro.santilli@arm.com def buildBinOp(name, base, opClass, op): 58213979Sciro.santilli@arm.com ''' 58313979Sciro.santilli@arm.com Create backported aarch64 instructions that use fplib. 58413979Sciro.santilli@arm.com 58513979Sciro.santilli@arm.com Because they are backported, these instructions are unconditional. 58613979Sciro.santilli@arm.com ''' 58713979Sciro.santilli@arm.com global header_output, decoder_output, exec_output 58813979Sciro.santilli@arm.com inst_datas = [ 58913979Sciro.santilli@arm.com ( 59013979Sciro.santilli@arm.com "s", 59113979Sciro.santilli@arm.com ''' 59213979Sciro.santilli@arm.com FpDest_uw = fplib%(op)s<>(FpOp1_uw, FpOp2_uw, fpscr); 59313979Sciro.santilli@arm.com ''' 59413979Sciro.santilli@arm.com ), 59513979Sciro.santilli@arm.com ( 59613979Sciro.santilli@arm.com "d", 59713979Sciro.santilli@arm.com ''' 59813979Sciro.santilli@arm.com uint64_t op1 = ((uint64_t)FpOp1P0_uw | 59913979Sciro.santilli@arm.com ((uint64_t)FpOp1P1_uw << 32)); 60013979Sciro.santilli@arm.com uint64_t op2 = ((uint64_t)FpOp2P0_uw | 60113979Sciro.santilli@arm.com ((uint64_t)FpOp2P1_uw << 32)); 60213979Sciro.santilli@arm.com uint64_t dest = fplib%(op)s<>(op1, op2, fpscr); 60313979Sciro.santilli@arm.com FpDestP0_uw = dest; 60413979Sciro.santilli@arm.com FpDestP1_uw = dest >> 32; 60513979Sciro.santilli@arm.com ''' 60613979Sciro.santilli@arm.com ) 60713979Sciro.santilli@arm.com ] 60813979Sciro.santilli@arm.com Name = name[0].upper() + name[1:] 60913979Sciro.santilli@arm.com declareTempl = eval(base + "Declare"); 61013979Sciro.santilli@arm.com constructorTempl = eval(base + "Constructor"); 61113979Sciro.santilli@arm.com for size_suffix, code in inst_datas: 61213979Sciro.santilli@arm.com code = ( 61313979Sciro.santilli@arm.com ''' 61413979Sciro.santilli@arm.com FPSCR fpscr = (FPSCR)FpscrExc; 61513979Sciro.santilli@arm.com ''' + 61613979Sciro.santilli@arm.com code + 61713979Sciro.santilli@arm.com ''' 61813979Sciro.santilli@arm.com FpscrExc = fpscr; 61913979Sciro.santilli@arm.com ''' 62013979Sciro.santilli@arm.com ) 62113979Sciro.santilli@arm.com iop = InstObjParams( 62213979Sciro.santilli@arm.com name + size_suffix, 62313979Sciro.santilli@arm.com Name + size_suffix.upper(), 62413979Sciro.santilli@arm.com base, 62513979Sciro.santilli@arm.com { 62613979Sciro.santilli@arm.com "code": code % {"op": op}, 62713979Sciro.santilli@arm.com "op_class": opClass 62813979Sciro.santilli@arm.com }, 62913979Sciro.santilli@arm.com [] 63013979Sciro.santilli@arm.com ) 63113979Sciro.santilli@arm.com header_output += declareTempl.subst(iop) 63213979Sciro.santilli@arm.com decoder_output += constructorTempl.subst(iop) 63313979Sciro.santilli@arm.com exec_output += BasicExecute.subst(iop) 63413979Sciro.santilli@arm.com ops = [ 63513979Sciro.santilli@arm.com ("vminnm", "FpRegRegRegOp", "SimdFloatCmpOp", "MinNum"), 63613979Sciro.santilli@arm.com ("vmaxnm", "FpRegRegRegOp", "SimdFloatCmpOp", "MaxNum"), 63713979Sciro.santilli@arm.com ] 63813979Sciro.santilli@arm.com for op in ops: 63913979Sciro.santilli@arm.com buildBinOp(*op) 64013979Sciro.santilli@arm.com 6417760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 6427396Sgblack@eecs.umich.edu if doubleOp is None: 6437396Sgblack@eecs.umich.edu doubleOp = singleOp 6447396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 6457367Sgblack@eecs.umich.edu 6467396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 6477396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 6487396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 6497760SGiacomo.Gabrielli@arm.com { "code": code, 6507760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6517760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6527396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 6537396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 6547396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6557760SGiacomo.Gabrielli@arm.com { "code": code, 6567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6577760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6587368Sgblack@eecs.umich.edu 6597396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6607396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6617368Sgblack@eecs.umich.edu 6627396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6637396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6647396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6657396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6667369Sgblack@eecs.umich.edu 6677760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 6687760SGiacomo.Gabrielli@arm.com "sqrt") 6697369Sgblack@eecs.umich.edu 6707760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 6717760SGiacomo.Gabrielli@arm.com doubleOp = None): 6727396Sgblack@eecs.umich.edu if doubleOp is None: 6737396Sgblack@eecs.umich.edu doubleOp = singleOp 6747396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 6757369Sgblack@eecs.umich.edu 6767396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 6777783SGiacomo.Gabrielli@arm.com { "code": singleSimpleCode % { "op": singleOp }, 6787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6797760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6807396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6817396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 6827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6837760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6847369Sgblack@eecs.umich.edu 6857396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6867396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6877396Sgblack@eecs.umich.edu 6887396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6897396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6907396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6917396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6927396Sgblack@eecs.umich.edu 6937760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 6948588Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)") 6957760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 6968588Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))") 69711671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintp", "VRIntP", "FpRegRegOp", "SimdFloatMiscOp", 69811671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_POSINF, false, fpscr)", 69911671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 70011671Smitch.hayenga@arm.com "FPRounding_POSINF, false, fpscr)" 70111671Smitch.hayenga@arm.com ) 70211671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintm", "VRIntM", "FpRegRegOp", "SimdFloatMiscOp", 70311671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_NEGINF, false, fpscr)", 70411671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 70511671Smitch.hayenga@arm.com "FPRounding_NEGINF, false, fpscr)" 70611671Smitch.hayenga@arm.com ) 70711671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrinta", "VRIntA", "FpRegRegOp", "SimdFloatMiscOp", 70811671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEAWAY, false, fpscr)", 70911671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 71011671Smitch.hayenga@arm.com "FPRounding_TIEAWAY, false, fpscr)" 71111671Smitch.hayenga@arm.com ) 71211671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintn", "VRIntN", "FpRegRegOp", "SimdFloatMiscOp", 71311671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEEVEN, false, fpscr)", 71411671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 71511671Smitch.hayenga@arm.com "FPRounding_TIEEVEN, false, fpscr)" 71611671Smitch.hayenga@arm.com ) 7177381Sgblack@eecs.umich.edu}}; 7187381Sgblack@eecs.umich.edu 7197381Sgblack@eecs.umich.edulet {{ 7207381Sgblack@eecs.umich.edu 7217381Sgblack@eecs.umich.edu header_output = "" 7227381Sgblack@eecs.umich.edu decoder_output = "" 7237381Sgblack@eecs.umich.edu exec_output = "" 7247370Sgblack@eecs.umich.edu 7257640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 7267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7277396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7287639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7297639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 7307639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7317783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7327370Sgblack@eecs.umich.edu ''' 7337396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 7347370Sgblack@eecs.umich.edu { "code": vmlaSCode, 7357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7367760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7377396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 7387396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 7397370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 7407370Sgblack@eecs.umich.edu 7417640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 7427783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7438588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7448588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7457639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7468588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 7477639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 7487639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7498588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7508588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7527370Sgblack@eecs.umich.edu ''' 7537396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 7547370Sgblack@eecs.umich.edu { "code": vmlaDCode, 7557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7567760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7577396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 7587396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 7597370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 7607370Sgblack@eecs.umich.edu 7617640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 7627783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7637396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7647639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7657639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 7667639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7677783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7687370Sgblack@eecs.umich.edu ''' 7697396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 7707370Sgblack@eecs.umich.edu { "code": vmlsSCode, 7717760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7727760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7737396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 7747396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 7757370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 7767370Sgblack@eecs.umich.edu 7777640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 7787783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7798588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7808588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7817639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7828588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 7837639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7847639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7858588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7868588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7877783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7887370Sgblack@eecs.umich.edu ''' 7897396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 7907370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7917760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7927760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7937396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 7947396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 7957370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7967371Sgblack@eecs.umich.edu 7977640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 7987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7997396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 8007639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 8017639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 8027639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 8037783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8047371Sgblack@eecs.umich.edu ''' 8057396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 8067371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 8077760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8087760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 8097396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 8107396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 8117371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 8127371Sgblack@eecs.umich.edu 8137640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 8147783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8158588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8168588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8177639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 8188588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 8197639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 8207639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 8218588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8228588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8237783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8247371Sgblack@eecs.umich.edu ''' 8257396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 8267371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 8277760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8287760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 8297396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 8307396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 8317371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 8327371Sgblack@eecs.umich.edu 8337640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 8347783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8357396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 8367639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 8377639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 8387639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 8397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8407371Sgblack@eecs.umich.edu ''' 8417396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 8427760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 8437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 8457396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 8467396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 8477371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 8487371Sgblack@eecs.umich.edu 8497640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 8507783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8518588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8528588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8537639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 8548588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 8557639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 8567639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 8578588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8588588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8597783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8607371Sgblack@eecs.umich.edu ''' 8617396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 8627760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 8637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8647760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 8657396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 8667396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 8677371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 8687371Sgblack@eecs.umich.edu 8697640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 8707783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8717639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 8727639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 8737783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8747371Sgblack@eecs.umich.edu ''' 8757396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 8767760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 8777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8797396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 8807396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 8817371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8827371Sgblack@eecs.umich.edu 8837640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 8847783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8858588Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8868588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8877639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 8887639Sgblack@eecs.umich.edu fpscr.rMode); 8898588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8908588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8917783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8927371Sgblack@eecs.umich.edu ''' 8937396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 8947371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8957760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8967760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8977396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 8987396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 8997371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 9007381Sgblack@eecs.umich.edu}}; 9017381Sgblack@eecs.umich.edu 9027381Sgblack@eecs.umich.edulet {{ 9037381Sgblack@eecs.umich.edu 9047381Sgblack@eecs.umich.edu header_output = "" 9057381Sgblack@eecs.umich.edu decoder_output = "" 9067381Sgblack@eecs.umich.edu exec_output = "" 9077373Sgblack@eecs.umich.edu 9087640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 9097783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9107397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9118588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 9128588Sgblack@eecs.umich.edu FpDest = FpOp1_uw; 9137381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9147639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9167373Sgblack@eecs.umich.edu ''' 9177396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 9187373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 9197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9217396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 9227396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 9237373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 9247373Sgblack@eecs.umich.edu 9257640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 9267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9288588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw)); 9298588Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0_uw; 9307397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9317639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9328588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 9338588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 9347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9357373Sgblack@eecs.umich.edu ''' 9367396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 9377373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 9387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9407396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 9417396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 9427373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 9437373Sgblack@eecs.umich.edu 9447640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 9457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9467397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9478588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 9488588Sgblack@eecs.umich.edu FpDest = FpOp1_sw; 9497381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9507639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9527373Sgblack@eecs.umich.edu ''' 9537396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 9547373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 9557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9567760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9577396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 9587396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 9597373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 9607373Sgblack@eecs.umich.edu 9617640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 9627783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9637397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9648588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw)); 9658588Sgblack@eecs.umich.edu double cDest = FpOp1P0_sw; 9667397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9677639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9688588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 9698588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 9707783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9717373Sgblack@eecs.umich.edu ''' 9727396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 9737373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9747760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9757760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9767396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9777396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9787373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9797373Sgblack@eecs.umich.edu 9807640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 9817783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9827397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9837397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9847381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 98510037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0, false); 9868588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 9877639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9887783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9897380Sgblack@eecs.umich.edu ''' 9907396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 9917380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9927760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9937760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9947396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9957396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9967380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9977380Sgblack@eecs.umich.edu 9987640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 9997783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10008588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10017397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10027397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10037397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 100410037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0, false); 10057381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10067639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10078588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10087783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10097380Sgblack@eecs.umich.edu ''' 10107396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 10117380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 10127760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10137760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10147396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 10157396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 10167380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 10177380Sgblack@eecs.umich.edu 10187640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 10197783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10207397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10217397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10227381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 102310037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0, false); 10248588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 10257639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10267783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10277380Sgblack@eecs.umich.edu ''' 10287396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 10297380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 10307760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10317760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10327396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 10337396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 10347380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 10357380Sgblack@eecs.umich.edu 10367640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 10377783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10388588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10397397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10407397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10417397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 104210037SARM gem5 Developers int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0, false); 10437381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10447639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10458588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10467783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10477380Sgblack@eecs.umich.edu ''' 10487396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 10497380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 10507760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10517760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10527396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 10537396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 10547380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 10557380Sgblack@eecs.umich.edu 105613738Sciro.santilli@arm.com round_mode_suffix_to_mode = { 105713738Sciro.santilli@arm.com '': 'VfpRoundZero', 105813738Sciro.santilli@arm.com 'a': 'VfpRoundAway', 105913738Sciro.santilli@arm.com 'm': 'VfpRoundDown', 106013738Sciro.santilli@arm.com 'n': 'VfpRoundNearest', 106113738Sciro.santilli@arm.com 'p': 'VfpRoundUpward', 106213738Sciro.santilli@arm.com } 106313738Sciro.santilli@arm.com 106413738Sciro.santilli@arm.com def buildVcvt(code, className, roundModeSuffix): 106513738Sciro.santilli@arm.com global header_output, decoder_output, exec_output, \ 106613738Sciro.santilli@arm.com vfpEnabledCheckCode, round_mode_suffix_to_mode 106713738Sciro.santilli@arm.com full_code = vfpEnabledCheckCode + code.format( 106813738Sciro.santilli@arm.com round_mode=round_mode_suffix_to_mode[roundModeSuffix], 106913738Sciro.santilli@arm.com ) 107013738Sciro.santilli@arm.com iop = InstObjParams( 107113738Sciro.santilli@arm.com "vcvt{}".format(roundModeSuffix), 107213738Sciro.santilli@arm.com className.format(roundModeSuffix), 107313738Sciro.santilli@arm.com "FpRegRegOp", 107413738Sciro.santilli@arm.com { "code": full_code, 107513738Sciro.santilli@arm.com "predicate_test": predicateTest, 107613738Sciro.santilli@arm.com "op_class": "SimdFloatCvtOp" }, 107713738Sciro.santilli@arm.com [] 107813738Sciro.santilli@arm.com ) 107913738Sciro.santilli@arm.com header_output += FpRegRegOpDeclare.subst(iop); 108013738Sciro.santilli@arm.com decoder_output += FpRegRegOpConstructor.subst(iop); 108113738Sciro.santilli@arm.com exec_output += PredOpExecute.subst(iop); 108213738Sciro.santilli@arm.com 108313738Sciro.santilli@arm.com code = ''' 10847783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10857397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10877380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 108913738Sciro.santilli@arm.com FpDest_uw = vfpFpToFixed<float>( 109013738Sciro.santilli@arm.com FpOp1, false, 32, 0, true, {round_mode}); 10918588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 10927639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10947373Sgblack@eecs.umich.edu ''' 109513738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 109613738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpUIntS", round_mode_suffix) 10977373Sgblack@eecs.umich.edu 109813738Sciro.santilli@arm.com code = ''' 10997783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11008588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 11017397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 11027397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11037380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 11047397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 110513738Sciro.santilli@arm.com uint64_t result = vfpFpToFixed<double>( 110613738Sciro.santilli@arm.com cOp1, false, 32, 0, true, {round_mode}); 11077381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 11087639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11098588Sgblack@eecs.umich.edu FpDestP0_uw = result; 11107783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11117373Sgblack@eecs.umich.edu ''' 111213738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 111313738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpUIntD", round_mode_suffix) 11147373Sgblack@eecs.umich.edu 111513738Sciro.santilli@arm.com code = ''' 11167783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11177397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11187397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11197380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 11207381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 112113738Sciro.santilli@arm.com FpDest_sw = vfpFpToFixed<float>( 112213738Sciro.santilli@arm.com FpOp1, true, 32, 0, true, {round_mode}); 11238588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 11247639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11257783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11267373Sgblack@eecs.umich.edu ''' 112713738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 112813738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpSIntS", round_mode_suffix) 11297373Sgblack@eecs.umich.edu 113013738Sciro.santilli@arm.com code = ''' 11317783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11328588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 11337397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 11347397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11357380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 11367397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 113713738Sciro.santilli@arm.com int64_t result = vfpFpToFixed<double>( 113813738Sciro.santilli@arm.com cOp1, true, 32, 0, true, {round_mode}); 11397381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 11407639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11418588Sgblack@eecs.umich.edu FpDestP0_uw = result; 11427783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11437373Sgblack@eecs.umich.edu ''' 114413738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 114513738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpSIntD", round_mode_suffix) 11467374Sgblack@eecs.umich.edu 11477640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 11487783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11507397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11517381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11527783SGiacomo.Gabrielli@arm.com double cDest = fixFpSFpDDest(FpscrExc, FpOp1); 11537397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 11547639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11558588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 11568588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 11577783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11587374Sgblack@eecs.umich.edu ''' 11597396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 11607374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 11617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11627760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11637396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 11647396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 11657374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 11667374Sgblack@eecs.umich.edu 11677640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 11687783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11698588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 11707397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 11717397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11727397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 11737783SGiacomo.Gabrielli@arm.com FpDest = fixFpDFpSDest(FpscrExc, cOp1); 11747381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11757639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11767783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11777374Sgblack@eecs.umich.edu ''' 11787396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 11797374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 11807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11827396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 11837396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 11847374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 11857377Sgblack@eecs.umich.edu 11867640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 11877783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11887398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11897398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11907398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11917639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11927639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 11937398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11947639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11957783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11967398Sgblack@eecs.umich.edu ''' 11977398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 11987398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 12017398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 12027398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 12037398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 12047398Sgblack@eecs.umich.edu 12057640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 12067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12077398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12087398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12097639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 12107639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 12117398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 12127639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12147398Sgblack@eecs.umich.edu ''' 12157398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 12167398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 12177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 12197398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 12207398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 12217398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 12227398Sgblack@eecs.umich.edu 12237640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 12247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12257398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12267398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12278588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 12288588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 12298588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 31, 16,, 12307639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 12317639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 12328588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 12337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12357398Sgblack@eecs.umich.edu ''' 12367398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 12377398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 12387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 12407398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 12417398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 12427398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 12437398Sgblack@eecs.umich.edu 12447640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 12457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12467398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12477398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12488588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 12498588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 12508588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 15, 0, 12517639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 12527639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 12538588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 12547639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12557783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12567398Sgblack@eecs.umich.edu ''' 12577398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 12587398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 12597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 12617398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 12627398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 12637398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 12647398Sgblack@eecs.umich.edu 12657640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 12667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12677397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 12687377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12697377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12707377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12717377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12727377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12737377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12747377Sgblack@eecs.umich.edu } else { 12757389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 12767389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 12777396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 12787389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 12797396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 12807389Sgblack@eecs.umich.edu if (signal1 || signal2) 12817389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12827377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12837377Sgblack@eecs.umich.edu } 12847643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12857783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12867377Sgblack@eecs.umich.edu ''' 12877396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 12887377Sgblack@eecs.umich.edu { "code": vcmpSCode, 12897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12907760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12917396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 12927396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 12937377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 12947377Sgblack@eecs.umich.edu 12957640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 12968588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 12978588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12997397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 13007397Sgblack@eecs.umich.edu if (cDest == cOp1) { 13017377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13027397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 13037377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13047397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 13057377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13067377Sgblack@eecs.umich.edu } else { 13077389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 13087397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 13097397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 13107397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 13117397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 13127389Sgblack@eecs.umich.edu if (signal1 || signal2) 13137389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13147377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13157377Sgblack@eecs.umich.edu } 13167643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13177783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13187377Sgblack@eecs.umich.edu ''' 13197396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 13207377Sgblack@eecs.umich.edu { "code": vcmpDCode, 13217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13227760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13237396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 13247396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 13257377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 13267377Sgblack@eecs.umich.edu 13277640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 13287783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13297397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 13307389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 13317389Sgblack@eecs.umich.edu assert(imm == 0); 13327377Sgblack@eecs.umich.edu if (FpDest == imm) { 13337377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13347377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 13357377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13367377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 13377377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13387377Sgblack@eecs.umich.edu } else { 13397389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 13407389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 13417396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 13427389Sgblack@eecs.umich.edu if (signal) 13437389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13447377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13457377Sgblack@eecs.umich.edu } 13467643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13477783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13487377Sgblack@eecs.umich.edu ''' 13497396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 13507377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 13517760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13527760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13537396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 13547396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 13557377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 13567377Sgblack@eecs.umich.edu 13577640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 13587389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 13597389Sgblack@eecs.umich.edu assert(imm == 0); 13608588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13617783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13627397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 13637397Sgblack@eecs.umich.edu if (cDest == imm) { 13647377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13657397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13667377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13677397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13687377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13697377Sgblack@eecs.umich.edu } else { 13707389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 13717397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 13727397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 13737389Sgblack@eecs.umich.edu if (signal) 13747389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13757377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13767377Sgblack@eecs.umich.edu } 13777643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13787783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13797377Sgblack@eecs.umich.edu ''' 13807396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 13817377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 13827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13847396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 13857396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 13867377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 13877389Sgblack@eecs.umich.edu 13887640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 13897783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13907397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 13917389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 13927389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13937389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 13947389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13957389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 13967389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13977389Sgblack@eecs.umich.edu } else { 13987389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13997389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 14007389Sgblack@eecs.umich.edu } 14017643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14027783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14037389Sgblack@eecs.umich.edu ''' 14047396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 14057389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 14067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 14097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 14107389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 14117389Sgblack@eecs.umich.edu 14127640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 14138588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 14148588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 14157783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14167397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 14177397Sgblack@eecs.umich.edu if (cDest == cOp1) { 14187389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 14197397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 14207389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 14217397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 14227389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 14237389Sgblack@eecs.umich.edu } else { 14247389Sgblack@eecs.umich.edu fpscr.ioc = 1; 14257389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 14267389Sgblack@eecs.umich.edu } 14277643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14287783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14297389Sgblack@eecs.umich.edu ''' 14307396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 14317389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 14327760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14337760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14347396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 14357396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 14367389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 14377389Sgblack@eecs.umich.edu 14387640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 14397783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14407397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 14417389Sgblack@eecs.umich.edu if (FpDest == imm) { 14427389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 14437389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 14447389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 14457389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 14467389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 14477389Sgblack@eecs.umich.edu } else { 14487389Sgblack@eecs.umich.edu fpscr.ioc = 1; 14497389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 14507389Sgblack@eecs.umich.edu } 14517643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14527783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14537389Sgblack@eecs.umich.edu ''' 14547396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 14557389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 14567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14577760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14587396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 14597396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 14607389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 14617389Sgblack@eecs.umich.edu 14627640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 14638588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 14647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14657397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 14667397Sgblack@eecs.umich.edu if (cDest == imm) { 14677389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 14687397Sgblack@eecs.umich.edu } else if (cDest < imm) { 14697389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 14707397Sgblack@eecs.umich.edu } else if (cDest > imm) { 14717389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 14727389Sgblack@eecs.umich.edu } else { 14737389Sgblack@eecs.umich.edu fpscr.ioc = 1; 14747389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 14757389Sgblack@eecs.umich.edu } 14767643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14777783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14787389Sgblack@eecs.umich.edu ''' 14797396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 14807389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 14817760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14827760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14837396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 14847396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 14857389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 14867322Sgblack@eecs.umich.edu}}; 14877379Sgblack@eecs.umich.edu 14887379Sgblack@eecs.umich.edulet {{ 14897379Sgblack@eecs.umich.edu 14907379Sgblack@eecs.umich.edu header_output = "" 14917379Sgblack@eecs.umich.edu decoder_output = "" 14927379Sgblack@eecs.umich.edu exec_output = "" 14937379Sgblack@eecs.umich.edu 149411671Smitch.hayenga@arm.com vselSCode = vfpEnabledCheckCode + ''' 149511671Smitch.hayenga@arm.com if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) { 149611671Smitch.hayenga@arm.com FpDest = FpOp1; 149711671Smitch.hayenga@arm.com } else { 149811671Smitch.hayenga@arm.com FpDest = FpOp2; 149911671Smitch.hayenga@arm.com } ''' 150011671Smitch.hayenga@arm.com 150111671Smitch.hayenga@arm.com vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp", 150211671Smitch.hayenga@arm.com { "code" : vselSCode, 150311671Smitch.hayenga@arm.com "predicate_test" : predicateTest, 150411671Smitch.hayenga@arm.com "op_class" : "SimdFloatCmpOp" }, [] ) 150511671Smitch.hayenga@arm.com header_output += FpRegRegRegCondOpDeclare.subst(vselSIop); 150611671Smitch.hayenga@arm.com decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop); 150711671Smitch.hayenga@arm.com exec_output += PredOpExecute.subst(vselSIop); 150811671Smitch.hayenga@arm.com 150911671Smitch.hayenga@arm.com vselDCode = vfpEnabledCheckCode + ''' 151011671Smitch.hayenga@arm.com if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) { 151111671Smitch.hayenga@arm.com FpDestP0_uw = FpOp1P0_uw; 151211671Smitch.hayenga@arm.com FpDestP1_uw = FpOp1P1_uw; 151311671Smitch.hayenga@arm.com } else { 151411671Smitch.hayenga@arm.com FpDestP0_uw = FpOp2P0_uw; 151511671Smitch.hayenga@arm.com FpDestP1_uw = FpOp2P1_uw; 151611671Smitch.hayenga@arm.com } ''' 151711671Smitch.hayenga@arm.com 151811671Smitch.hayenga@arm.com vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp", 151911671Smitch.hayenga@arm.com { "code" : vselDCode, 152011671Smitch.hayenga@arm.com "predicate_test" : predicateTest, 152111671Smitch.hayenga@arm.com "op_class" : "SimdFloatCmpOp" }, [] ) 152211671Smitch.hayenga@arm.com header_output += FpRegRegRegCondOpDeclare.subst(vselDIop); 152311671Smitch.hayenga@arm.com decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop); 152411671Smitch.hayenga@arm.com exec_output += PredOpExecute.subst(vselDIop); 152511671Smitch.hayenga@arm.com}}; 152611671Smitch.hayenga@arm.com 152711671Smitch.hayenga@arm.com 152811671Smitch.hayenga@arm.comlet {{ 152911671Smitch.hayenga@arm.com 153011671Smitch.hayenga@arm.com header_output = "" 153111671Smitch.hayenga@arm.com decoder_output = "" 153211671Smitch.hayenga@arm.com exec_output = "" 153311671Smitch.hayenga@arm.com 15347640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 15357783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15367397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15377397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15387381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 153910037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm); 15408588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 15417639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15427783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15437379Sgblack@eecs.umich.edu ''' 15447396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 15457379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 15467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15477760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15487396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 15497396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 15507379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 15517379Sgblack@eecs.umich.edu 15527640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 15537783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15548588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15557397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15567397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15577397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 155810037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, true, 32, imm); 15597381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15607639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15618588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 15628588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 15637783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15647379Sgblack@eecs.umich.edu ''' 15657396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 15667379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 15677760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15687760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15697396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 15707396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 15717379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 15727379Sgblack@eecs.umich.edu 15737640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 15747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15757397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15767397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15777381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 157810037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, imm); 15798588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 15807639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15817783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15827379Sgblack@eecs.umich.edu ''' 15837396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 15847379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 15857760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15867760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15877396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 15887396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 15897379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 15907379Sgblack@eecs.umich.edu 15917640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 15927783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15938588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15947397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15957397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15967397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 159710037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 32, imm); 15987381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15997639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16008588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 16018588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 16027783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16037379Sgblack@eecs.umich.edu ''' 16047396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 16057379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 16067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16087396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 16097396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 16107379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 16117379Sgblack@eecs.umich.edu 16127640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 16137783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16147397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16158588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 161610037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, 32, imm); 16177381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16187639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16197783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16207379Sgblack@eecs.umich.edu ''' 16217396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 16227379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 16237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16257396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 16267396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 16277379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 16287379Sgblack@eecs.umich.edu 16297640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 16307783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16318588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 16327397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16337381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 163410037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 16357397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16367639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16378588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 16388588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 16397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16407379Sgblack@eecs.umich.edu ''' 16417396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 16427379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 16437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16457396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 16467396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 16477379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 16487379Sgblack@eecs.umich.edu 16497640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 16507783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16517397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16528588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 165310037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, 32, imm); 16547381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16557639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16567783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16577379Sgblack@eecs.umich.edu ''' 16587396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 16597379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 16607760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16617760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16627396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 16637396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 16647379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 16657379Sgblack@eecs.umich.edu 16667640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 16677783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16688588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 16697397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 167110037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 16727397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16748588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 16758588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 16767783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16777379Sgblack@eecs.umich.edu ''' 16787396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 16797379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 16807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16827396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 16837396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 16847379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 16857379Sgblack@eecs.umich.edu 16867640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 16877783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16887397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 16897397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16907381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 169110037SARM gem5 Developers FpDest_sh = vfpFpToFixed<float>(FpOp1, true, 16, imm); 16928588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sh)); 16937639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16957379Sgblack@eecs.umich.edu ''' 16967379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 16977396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16987379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 16997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17017396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 17027396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 17037379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 17047379Sgblack@eecs.umich.edu 17057640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 17067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17078588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 17087397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 17097397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17107397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 171110037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, true, 16, imm); 17127381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 17137639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17148588Sgblack@eecs.umich.edu FpDestP0_uw = result; 17158588Sgblack@eecs.umich.edu FpDestP1_uw = result >> 32; 17167783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17177379Sgblack@eecs.umich.edu ''' 17187379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 17197396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17207379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 17217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17227760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17237396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 17247396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 17257379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 17267379Sgblack@eecs.umich.edu 17277640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 17287783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17297397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 17307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17317381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 173210037SARM gem5 Developers FpDest_uh = vfpFpToFixed<float>(FpOp1, false, 16, imm); 17338588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uh)); 17347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17357783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17367379Sgblack@eecs.umich.edu ''' 17377379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 17387396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17397379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 17407760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17417760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17427396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 17437396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 17447379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 17457379Sgblack@eecs.umich.edu 17467640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 17477783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17488588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 17497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 17507397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17517397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 175210037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 16, imm); 17537381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 17547639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17558588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 17568588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 17577783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17587379Sgblack@eecs.umich.edu ''' 17597379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 17607396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17617379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 17627760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17637760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17647396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 17657396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 17667379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 17677379Sgblack@eecs.umich.edu 17687640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 17697783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17707397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17718588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); 177210037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, 16, imm); 17737381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 17747639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17757783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17767379Sgblack@eecs.umich.edu ''' 17777379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 17787396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17797379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 17807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17827396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 17837396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 17847379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 17857379Sgblack@eecs.umich.edu 17867640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 17877783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17888588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 17897397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17907381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 179110037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 17927397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 17937639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17948588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 17958588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 17967783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17977379Sgblack@eecs.umich.edu ''' 17987379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 17997396Sgblack@eecs.umich.edu "FpRegRegImmOp", 18007379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 18017760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 18027760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 18037396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 18047396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 18057379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 18067379Sgblack@eecs.umich.edu 18077640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 18087783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 18097397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 18108588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); 181110037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, 16, imm); 18127381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 18137639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 18147783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 18157379Sgblack@eecs.umich.edu ''' 18167379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 18177396Sgblack@eecs.umich.edu "FpRegRegImmOp", 18187379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 18197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 18207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 18217396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 18227396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 18237379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 18247379Sgblack@eecs.umich.edu 18257640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 18267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 18278588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 18287397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 18297381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 183010037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 18317397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 18327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 18338588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 18348588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 18357783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 18367379Sgblack@eecs.umich.edu ''' 18377379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 18387396Sgblack@eecs.umich.edu "FpRegRegImmOp", 18397379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 18407760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 18417760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 18427396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 18437396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 18447379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 18457379Sgblack@eecs.umich.edu}}; 1846