Searched hist:2009 (Results 726 - 750 of 951) sorted by relevance
/gem5/src/python/m5/util/ | ||
H A D | convert.py | 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. |
/gem5/src/python/m5/ | ||
H A D | ticks.py | diff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. |
/gem5/tests/configs/ | ||
H A D | memtest-ruby.py | diff 6836:1a01f799bd76 Fri Sep 11 17:22:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: cleaned up unified MESI/MOESI configuration diff 6798:289ac904233d Wed Nov 18 21:00:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> m5: refreshed the ruby memtest regression stats diff 6289:a9e7d19871b5 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Fix RubyMemory to work with the newer ruby. 6166:6fad2d8345b7 Mon May 11 13:38:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Set up Ruby regression tests. |
H A D | t1000-simple-atomic.py | diff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. |
/gem5/configs/common/ | ||
H A D | FSConfig.py | diff 6802:e649cb8af113 Sat Dec 19 04:49:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Record the memory mode when building an X86 system. diff 6765:b5101309174d Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Support for merging ALPHA_FS and ruby Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports. diff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. diff 6135:9327451a8e7a Sun Apr 26 05:04:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. diff 6074:76c2b55fce6d Sun Apr 19 07:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Actually put the PCI INTA entry into the MP tables. diff 6072:2372a164604f Sun Apr 19 07:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make E820 report nice, round (and correct) numbers. diff 6044:3b23e5fc76e4 Sun Apr 19 05:39:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Automatically make the IO APIC in an N CPU system have id N+1. diff 5918:c3d88393a1f3 Wed Feb 25 13:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add IRQ4 to the Intel MP tables. diff 5847:02e0e93d1ba7 Sun Feb 01 03:29:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Find the natural lpj for this configuration. diff 5845:c88856b98084 Sun Feb 01 03:27:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a root device to the kernel command line. |
/gem5/src/arch/arm/ | ||
H A D | process.cc | diff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array. When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. diff 6400:b7fd31c84c99 Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Set up the initial stack frame to match a recent Linux. diff 6020:0647c8b31a99 Mon Apr 06 13:19:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Merge ARM into the head. ARM will compile but may not actually work. 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
H A D | stacktrace.cc | 6757:d86d3d6e5326 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Boilerplate full-system code. |
H A D | pagetable.hh | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/mips/ | ||
H A D | stacktrace.cc | diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes. White space, commented out code, some other minor fixes. |
/gem5/src/cpu/pred/ | ||
H A D | 2bit_local.hh | 6226:f1076450ab2b Fri Jun 05 00:50:00 EDT 2009 Nathan Binkert <nate@binkert.org> move: put predictor includes and cc files into the same place |
/gem5/src/mem/cache/prefetch/ | ||
H A D | base.cc | diff 6665:874f2ee2f115 Sat Sep 26 13:50:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> Force prefetches to check cache and MSHRs immediately prior to issue. This prevents redundant prefetches from being issued, solving the occasional 'needsExclusive && !blk->isWritable()' assertion failure in cache_impl.hh that several people have run into. Eliminates "prefetch_cache_check_push" flag, neither setting of which really solved the problem. diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh diff 6105:a27c0934de24 Mon Apr 20 21:54:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> request: rename INST_READ to INST_FETCH. diff 5875:d82be3235ab4 Mon Feb 16 11:56:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Fixes to get prefetching working again. Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too. |
/gem5/src/sim/ | ||
H A D | process_impl.hh | diff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned |
H A D | process.hh | diff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array. When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh diff 6399:bf122a97f88b Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Elf: Add in some new aux vector type constants. diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header. This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh diff 5999:3cf8e71257e0 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: Fix all stats usages to deal with template fixes diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object. |
/gem5/src/arch/x86/linux/ | ||
H A D | process.cc | diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header. This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. diff 6075:1e1a874f9b17 Sun Apr 19 07:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SE mode: Make keeping track of the number of syscalls less hacky. diff 5956:a49d9413a9e8 Fri Feb 27 12:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Distinguish the width of values on the stack between 32 and 64 bit processes. diff 5955:d35d2b28df38 Fri Feb 27 12:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a class to support 32 bit x86 linux process. |
/gem5/src/mem/ | ||
H A D | page_table.hh | diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh diff 5877:9fe574944f31 Mon Feb 16 17:47:00 EST 2009 Lisa Hsu <hsul@eecs.umich.edu> sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. |
/gem5/src/cpu/ | ||
H A D | thread_state.cc | diff 6331:d947798df4a1 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. diff 6324:a535b2232c08 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Move the PCs out of the ISAs and into the CPUs. diff 6221:58a3c04e6344 Tue May 26 12:23:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: add a type for thread IDs and try to use it everywhere diff 6031:be16ad28822f Wed Apr 15 16:18:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ThreadState: initialize status to Halted in constructor. This provides a common initial status for all threads independent of CPU model (unlike the prior situation where CPUs initialized threads to inconsistent states). This mostly matters for SE mode; in FS mode, ISA-specific startupCPU() methods generally handle boot-time initialization of thread contexts (since the right thing to do is ISA-dependent). |
H A D | static_inst.hh | diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh diff 6192:6cd5f0282d8a Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder-tlb-cunit: merge the TLB as implicit to any memory access TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * * diff 5922:28bcb158eaae Wed Feb 25 13:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Add a flag to identify a read barrier to the static inst class. diff 5870:5645632d594c Wed Feb 11 01:19:00 EST 2009 Nathan Binkert <nate@binkert.org> style diff 5865:54ed46881217 Tue Feb 10 18:49:00 EST 2009 Korey Sewell <ksewell@umich.edu> CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | AbstractController.hh | diff 6846:60e0df8086f0 Thu Sep 17 18:39:00 EDT 2009 Polina Dudnik <pdudnik@cs.wisc.edu> Functionality migrated to sequencer. diff 6510:336a194c8500 Sat Aug 15 01:45:00 EDT 2009 pdudnik@gmail.com Made servicing_atomic a counter and added started writes: a function for setting the flag to indicate that the rmw_writes started issuing diff 6506:e9e7ca667575 Fri Aug 14 15:24:00 EDT 2009 pdudnik@gmail.com Multi-line RMW handling 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore. |
/gem5/src/base/ | ||
H A D | SConscript | diff 5952:c1ee8282291d Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> CPA: Add new object for gathering critical path annotations. diff 5887:6b312cafaa59 Mon Feb 23 03:22:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: get rid of the convoluted 'database' code. Just use the stuff directly and things ought to be more clear diff 5882:5a047c3f3795 Mon Feb 23 14:48:00 EST 2009 Nathan Binkert <nate@binkert.org> debug: Move debug_break into src/base diff 5800:19c06c037040 Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> tracing: Add help strings for some of the trace flags |
/gem5/src/dev/x86/ | ||
H A D | i8254.hh | diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections. |
H A D | cmos.hh | diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections. |
/gem5/src/arch/sparc/ | ||
H A D | process.cc | diff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array. When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. diff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s diff 6335:a08470cb53e5 Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Fold the MiscRegFile all the way into the ISA object. diff 6320:b90e13cafba4 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Phase out SPARC's intregfile.hh. diff 6110:5051aafec8d5 Tue Apr 21 11:17:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object. diff 5941:e8a1f956d76c Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame. |
H A D | tlb.cc | diff 6428:9e35cdc95e81 Sun Aug 02 01:50:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> Clean up some inconsistencies with Request flags. diff 6335:a08470cb53e5 Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Fold the MiscRegFile all the way into the ISA object. diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB diff 5894:8091ac99341a Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. diff 5891:73084c6bb183 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Replace the translate functions in the TLBs with translateAtomic. diff 5823:9f7efe90084e Fri Jan 30 20:04:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Errors: Use the correct panic/warn/fatal/info message in some places. |
/gem5/src/arch/ | ||
H A D | isa_parser.py | diff 6866:0dd40ed15354 Thu Nov 05 20:21:00 EST 2009 Nathan Binkert <nate@binkert.org> isa_parser: allow negative integer literals diff 6728:5037062422c8 Sun Nov 08 16:31:00 EST 2009 Nathan Binkert <nate@binkert.org> compile: wrap 64bit numbers with ULL() so 32bit compiles work In the isa_parser, we need to check case statements. diff 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. diff 6661:9bc3e4611009 Wed Sep 23 21:28:00 EDT 2009 Nathan Binkert <nate@binkert.org> isa_parser: Turn the ISA Parser into a subclass of Grammar. This is to prepare for future cleanup where we allow SCons to create a separate grammar class for each ISA diff 6655:380a32b43336 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access diff 6377:aac74ffc8ca2 Mon Jul 20 23:20:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> isa_parser: Get rid of the now unused ControlBitfieldOperand. diff 6338:14572c7334b5 Fri Jul 10 04:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISAs: Get rid of the IControl operand type. A separate operand type is not necessary to use two bitfields to generate the index. diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter. diff 6311:30d1e27daf68 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISA parser: Allow alternative read/write code for operands. diff 6178:2bbb49ca07a8 Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> isa-parser: made a few changes, but not author-worthy |
/gem5/src/arch/alpha/ | ||
H A D | process.cc | diff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array. When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. diff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned diff 6180:1a8950d566ff Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder-bpred: edits to handle non-delay-slot ISAs Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline diff 6110:5051aafec8d5 Tue Apr 21 11:17:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object. |
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