Searched hist:2009 (Results 476 - 500 of 951) sorted by relevance

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/gem5/src/arch/x86/
H A Dtlb.hhdiff 6141:5babc3f3d8c8 Sun Apr 26 19:48:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Split out the internal memory space from the regular translate() and precompute mode.
diff 6132:916f10213bea Thu Apr 23 04:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Put the StoreCheck flag with the others, and don't collide with other flags.
diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5895:569e3b31a868 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
diff 5894:8091ac99341a Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
diff 5891:73084c6bb183 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Replace the translate functions in the TLBs with translateAtomic.
diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
H A DX86TLB.pydiff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
H A Dpagetable_walker.ccdiff 6027:3d7c2fe13f6a Mon Apr 13 07:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix minor bug in the page table walker from TLB shuffling.
diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5904:5c61233cbd53 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a trace flag for the page table walker.
diff 5897:29cecf4fe602 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the timing mode of the page table walker.
diff 5895:569e3b31a868 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
/gem5/src/arch/x86/bios/
H A Dintelmp.ccdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
/gem5/src/cpu/pred/
H A D2bit_local.ccdiff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
6226:f1076450ab2b Fri Jun 05 00:50:00 EDT 2009 Nathan Binkert <nate@binkert.org> move: put predictor includes and cc files into the same place
/gem5/src/mem/ruby/common/
H A DSConscriptdiff 6168:ba6fe02228db Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false
6157:eaf2fd8f54c0 Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.
/gem5/src/sim/
H A Darguments.hhdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
H A Dsimulate.ccdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5823:9f7efe90084e Fri Jan 30 20:04:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Errors: Use the correct panic/warn/fatal/info message in some places.
/gem5/src/dev/x86/
H A Di8042.hhdiff 5832:38f3f3e1e442 Sun Feb 01 02:59:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Refactor and clean up the keyboard controller.
5831:ee307cca6d31 Sun Feb 01 02:59:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a keyboard controller device.
H A Di8259.hhdiff 6073:d552a9544974 Sun Apr 19 07:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Mask the PIC at startup to avoid a glitch which causes an NMI.
diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
H A Dcmos.ccdiff 5898:541097c69e22 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add makeAtomicResponse to the read/write functions of x86 devices.
diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
H A Di82094aa.hhdiff 6139:2bfd792b1cc0 Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement lowest priority interrupts more correctly.
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
diff 6137:d3ee4e0d690c Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APICs register themselves with the IO APIC.
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
diff 6136:4f8af2f3185f Sun Apr 26 05:06:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Record the initial APIC ID which identifies an APIC in M5.
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
diff 6135:9327451a8e7a Sun Apr 26 05:04:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
/gem5/src/mem/ruby/network/simple/
H A DSwitch.ccdiff 6493:1fa51760a963 Fri Aug 07 16:59:00 EDT 2009 Tushar Krishna <Tushar.Krishna@amd.com> bug fix for data_msg_size in network/Network.cc
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
H A DThrottle.hhdiff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/alpha/
H A Dtlb.hhdiff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5999:3cf8e71257e0 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: Fix all stats usages to deal with template fixes
diff 5894:8091ac99341a Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
diff 5891:73084c6bb183 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Replace the translate functions in the TLBs with translateAtomic.
/gem5/src/cpu/
H A Dsimple_thread.hhdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6418:4836ec6b73a1 Wed Jul 29 03:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Simple CPU: Make the simple CPU handle the IntRegs trace flag.
diff 6331:d947798df4a1 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6326:008930a4ace5 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined RegFile class.
diff 6324:a535b2232c08 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Move the PCs out of the ISAs and into the CPUs.
diff 6323:fd0f91f067d2 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM, Simple CPU: Fix an index and add assert checks.
diff 6316:51f3026d4cbb Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined integer register file.
diff 6315:c7295a4826d5 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined floating point register file.
diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter.
H A Dinteltrace.hhdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5784:8a28646c4bc2 Wed Jan 07 01:34:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Tracing: Make tracing aware of macro and micro ops.
/gem5/src/arch/arm/isa/formats/
H A Dfp.isadiff 6724:70129fdded75 Sun Nov 08 05:08:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Split the condition codes out of the CPSR.

This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
diff 6252:af2c9d9accda Sun Jun 21 20:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Remove the currently unecessary FPAOp class.
diff 6243:3a1698fbbc9f Sun Jun 21 12:37:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make the isa parser aware that CPSR is being used.
diff 6242:1cee707c1228 Sun Jun 21 12:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Pull some static code out of the isa desc and create miscregs.hh.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/mips/isa/
H A Ddecoder.isadiff 6810:4fc450d6a54e Thu Dec 31 15:30:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Implement the SE mode version of rdhwr.
diff 6809:d99f7b0ac614 Thu Dec 31 15:30:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Fix decoding of the rdhwr instruction.
diff 6385:743ddf69eeed Wed Jul 22 04:57:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Small fix I forgot to qrefresh into my last change.
diff 6384:5209002cb6d5 Wed Jul 22 04:51:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Style/formatting sweep of the decoder itself.
diff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
diff 6376:eaf61ef6a8f2 Mon Jul 20 23:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
diff 6076:e141cc7896ce Sun Apr 19 07:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Memory: Rename LOCKED for load locked store conditional to LLSC.
diff 6037:0b0341bfb359 Sat Apr 18 10:42:00 EDT 2009 Korey Sewell <ksewell@umich.edu> mips-syscall: mark with correct flag. \nMIPS was using wrong serialization flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall
diff 6036:f0841ee466a5 Sat Apr 18 10:42:00 EDT 2009 Korey Sewell <ksewell@umich.edu> o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly
/gem5/src/mem/ruby/system/
H A DDMASequencer.ccdiff 6467:5670eee2a866 Tue Aug 04 01:52:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate. They are:

1. Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2. DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
diff 6433:0f0f0fbef977 Mon Jul 27 22:43:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed unused/incorrect profiler state
diff 6369:82ac95f4d9f0 Sat Jul 18 18:40:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> merge
diff 6368:cecc7019b458 Sat Jul 18 18:03:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: fixed dma sequencer bug

The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't block aligned.
This changeset also includes a fix to MI_example for a similar bug.
diff 6355:79464d8a4d2f Mon Jul 13 18:22:00 EDT 2009 pdudnik@gmail.com 1. Got rid of unused functions in DirectoryMemory
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue

Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once
diff 6350:accdf59eedd3 Mon Jul 13 12:37:00 EDT 2009 pdudnik@gmail.com Replaced RMW with Locked. RMW will be used for the coherence-aided atomics other than LLSC
6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
/gem5/src/arch/arm/
H A Dutility.hhdiff 6759:98101a5f7ee4 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Begin implementing CP15
diff 6757:d86d3d6e5326 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Boilerplate full-system code.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6251:1d794d81a4e6 Sun Jun 21 19:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make inst bitfields accessible outside of the isa desc.
diff 6246:5744fafb5072 Sun Jun 21 12:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Clear out some inherited hangers on in util.isa and utility.hh.
diff 6242:1cee707c1228 Sun Jun 21 12:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Pull some static code out of the isa desc and create miscregs.hh.
diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/python/m5/
H A Dmain.pydiff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
diff 6171:59006a759508 Mon May 11 14:18:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: pull out common code from main that processes arguments
diff 5950:bf32d75419ad Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Trace: fix the --trace-start option
diff 5879:e9f9c0f7e5f0 Wed Feb 18 13:00:00 EST 2009 Nathan Binkert <nate@binkert.org> events: Make trace events happen at the right priority.
Also, while we're at it, remember that priorities are in the Event class
and add a disable method to disable tracing.
diff 5873:67a6ea624776 Sun Feb 15 23:39:00 EST 2009 Nathan Binkert <nate@binkert.org> traceflags: fix --trace-help
diff 5824:b88edb9f3333 Fri Jan 30 20:04:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> SCons: Fix how we get Mercurial revision information since internals keep changing.
diff 5802:1fb28f526602 Mon Jan 19 17:43:00 EST 2009 Nathan Binkert <nate@binkert.org> python: add fatal() function to the m5 package and use it
diff 5801:e0850da03cd4 Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> python: Try to isolate the stuff that's in the m5.internal package a bit more.
diff 5799:0af61da2b66a Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> tracing: panic() if people try to use tracing, but TRACING_ON is not set.
Also clean things up so that help strings can more easily be added.
Move the help function into trace.py
/gem5/tests/configs/
H A Do3-timing-ruby.pydiff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
diff 6289:a9e7d19871b5 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Fix RubyMemory to work with the newer ruby.
6166:6fad2d8345b7 Mon May 11 13:38:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Set up Ruby regression tests.
/gem5/src/arch/x86/insts/
H A Dstatic_inst.hhdiff 6361:62de7e765286 Fri Jul 17 21:49:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up a named constant for the "fold bit" for int register indices.
diff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 5787:e3a6f53818fe Wed Jan 07 01:46:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Move the function that prints memory args into the inst base class.
/gem5/src/arch/x86/isa/microops/
H A Dlimmop.isadiff 6524:e207990ddd14 Mon Aug 17 21:17:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lfpimm microop.
diff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 5788:6d4161a36ca1 Wed Jan 07 01:55:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Autogenerate macroop generateDisassemble function.

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