Searched hist:2009 (Results 326 - 350 of 951) sorted by relevance

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/gem5/src/python/m5/util/
H A D__init__.pydiff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
diff 6502:6c7d9e9b3c83 Sun Aug 16 16:40:00 EDT 2009 Nathan Binkert <nate@binkert.org> code_formatter: Add a python class for writing code generator templates
diff 6500:ee7587e7c71d Sun Aug 16 16:40:00 EDT 2009 Nathan Binkert <nate@binkert.org> orderdict: Use DictMixin and add orderdict to m5.util
diff 5873:67a6ea624776 Sun Feb 15 23:39:00 EST 2009 Nathan Binkert <nate@binkert.org> traceflags: fix --trace-help
/gem5/util/
H A Dslicc6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/mem/cache/prefetch/
H A Dspatio_temporal_memory_streaming.cc13786:860c780d9f30 Thu Mar 07 10:13:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the STeMS prefetcher

Reference:
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
Babak Falsafi. 2009. Spatio-temporal memory streaming.
In Proceedings of the 36th annual international symposium on
Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dspatio_temporal_memory_streaming.hh13786:860c780d9f30 Thu Mar 07 10:13:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the STeMS prefetcher

Reference:
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
Babak Falsafi. 2009. Spatio-temporal memory streaming.
In Proceedings of the 36th annual international symposium on
Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/ruby/system/
H A DSequencer.hhdiff 6859:5de565c4b7bd Wed Nov 18 12:55:00 EST 2009 Derek Hower <drh5@cs.wisc.edu> ruby: added sequencer stats to track what requests are waiting on
diff 6846:60e0df8086f0 Thu Sep 17 18:39:00 EDT 2009 Polina Dudnik <pdudnik@cs.wisc.edu> Functionality migrated to sequencer.
diff 6845:9740ade45962 Tue Sep 15 22:37:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: improve libruby_issue_request feedback
diff 6825:104115ebc206 Fri Aug 21 16:52:00 EDT 2009 pdudnik@gmail.com [mq]: first_patch
diff 6763:5a879a3513dc Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby 64-bit address output fixes.
diff 6505:a2306c563df2 Fri Aug 14 15:06:00 EDT 2009 pdudnik@gmail.com SMT atomics modifications:
don't allow enquing from other threads if servicing and atomic for a thread
diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6165:2d26c346f1be Mon May 11 13:38:00 EDT 2009 Daniel Sanchez <sanchezd@stanford.edu> ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
/gem5/src/arch/x86/
H A Dfaults.ccdiff 6222:9ee4a06a960b Fri May 29 02:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Keep track of more descriptor state to accomodate KVM.
diff 6140:7a2dc7d41ee1 Sun Apr 26 19:47:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Centralize updates to the handy M5 reg.
diff 6049:595b5016f6d5 Sun Apr 19 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the STARTUP IPI.
diff 6048:65a321a3a691 Sun Apr 19 05:53:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INIT IPI.
diff 5909:ecbd27e5d1f8 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a trace flag for tracing faults.
diff 5895:569e3b31a868 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
diff 5858:54f64fb1bd62 Sun Feb 01 20:09:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: All x86 fault classes now attempt to do something useful.
diff 5857:8cd8e1393990 Sun Feb 01 20:08:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the fault classes handle error codes better.
diff 5856:f770af5600c9 Sun Feb 01 20:07:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the long mode interrupt/exception microcode handle an error code.
H A Dinterrupts.ccdiff 6712:b95abe00dd9d Wed Nov 04 19:57:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix compile problems pointed out by gcc 4.4
diff 6138:6cbdd76b93db Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Tell the function that sends int messages who to send to instead of figuring it out itself.
diff 6137:d3ee4e0d690c Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APICs register themselves with the IO APIC.
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
diff 6136:4f8af2f3185f Sun Apr 26 05:06:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Record the initial APIC ID which identifies an APIC in M5.
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
diff 6069:cb5b778785a6 Sun Apr 19 07:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement broadcast IPIs.
diff 6066:a9fe0813039f Sun Apr 19 06:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Only recognize the first startup IPI after INIT or reset.
diff 6065:0ad264b74ac2 Sun Apr 19 06:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Use recvResponse to implement the idle bit in the Local APIC ICR.
diff 6064:46d327d42036 Sun Apr 19 06:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a function which gets called when an interrupt message has been delivered.
diff 6061:385c8482bf14 Sun Apr 19 06:47:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Keep track of the pioAddr for the local APIC.
diff 6050:852ba59fa8d9 Sun Apr 19 06:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: The startup IPI delivery mode is not reserved.
/gem5/src/arch/arm/
H A DSConscriptdiff 6757:d86d3d6e5326 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Boilerplate full-system code.
diff 6735:6437ad24a8a0 Tue Nov 10 23:34:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Implement fault classes.

Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
diff 6397:cb1d7c957f49 Mon Jul 27 03:51:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a native tracer.
diff 6333:9425c8a86e5c Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fold the MiscRegFile all the way into the ISA object.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6328:67dbc192f692 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Collapse ARM and MIPS regfile directories.
diff 6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
diff 6253:988a001820f8 Sun Jun 21 20:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Simplify the ISA desc by pulling some classes out of it.
diff 6246:5744fafb5072 Sun Jun 21 12:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Clear out some inherited hangers on in util.isa and utility.hh.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
H A Dtypes.hhdiff 6759:98101a5f7ee4 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Begin implementing CP15
diff 6749:ac658ad78659 Sat Nov 14 22:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a bitfield to indicate if an immediate should be used.
diff 6743:f9e317156e45 Sat Nov 14 12:25:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Move around decoder to properly decode CP15
diff 6741:73d89772f409 Wed Nov 11 02:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix some bugs in the ISA desc and fill out some instructions.
diff 6723:ea7c71a3433a Sun Nov 08 05:01:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add in more bits for the mon mode.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter.
diff 6275:4a392427117d Thu Jul 02 01:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of some bitfields that aren't used. A few may need to be readded.
diff 6269:8be7583b271c Thu Jul 02 01:11:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Decode some media instructions. These are untested.
diff 6268:0f869e59c079 Thu Jul 02 01:11:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Use the new DataOp format to simplify the decoder.
/gem5/src/dev/x86/
H A Di82094aa.ccdiff 6803:c647872c6590 Sat Dec 19 04:50:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.
diff 6712:b95abe00dd9d Wed Nov 04 19:57:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix compile problems pointed out by gcc 4.4
diff 6139:2bfd792b1cc0 Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement lowest priority interrupts more correctly.
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
diff 6138:6cbdd76b93db Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Tell the function that sends int messages who to send to instead of figuring it out itself.
diff 6137:d3ee4e0d690c Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APICs register themselves with the IO APIC.
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
diff 6136:4f8af2f3185f Sun Apr 26 05:06:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Record the initial APIC ID which identifies an APIC in M5.
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
diff 6135:9327451a8e7a Sun Apr 26 05:04:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
diff 6045:214461cb8abe Sun Apr 19 05:42:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make code that sends an interrupt from the IO APIC available for IPIs.
diff 5898:541097c69e22 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add makeAtomicResponse to the read/write functions of x86 devices.
diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
/gem5/src/arch/x86/isa/microops/
H A Dldstop.isadiff 6736:530e457c88c7 Mon Nov 09 01:49:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
diff 6624:b157ef23d76c Sun Aug 23 17:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Preserve the NO_ACCESS flag when giving CDA a specialized interface.
diff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 6132:916f10213bea Thu Apr 23 04:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Put the StoreCheck flag with the others, and don't collide with other flags.
diff 6080:50890791c591 Sun Apr 19 07:55:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the stul microop.
This microop does a store and unlocks the requested address. The RISC86
microop ISA doesn't seem to have an equivalent to this, so I'm guessing that
the store following an ldstl is automatically unlocking. We don't do it this
way for performance reasons since the behavior is the same.
diff 6079:f39c5598a302 Sun Apr 19 07:55:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the ldstl microop.
This microop does a load, checks that a store would succeed, and locks the
requested address.
diff 6056:4435d13700de Sun Apr 19 06:24:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: LEA calculates an address before segmentation.
diff 5969:815827deb469 Fri Feb 27 12:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take address size into account when computing an effective address.
diff 5965:71f8d7c12619 Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix segment limit checks.
diff 5920:5a9c976270d6 Wed Feb 25 13:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a basic prefetch instruction.
/gem5/src/arch/arm/linux/
H A Dprocess.ccdiff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array.

When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
diff 6640:30d92d2b66a1 Wed Sep 16 01:36:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Syscalls: Implement sysinfo() syscall.
diff 6421:1aa0b4673699 Wed Jul 29 03:18:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix an instruction in the cmpxchg kernel provided routine.
The instruction was encoded as a load instead of the intended store.
diff 6420:7d0e7547be5e Wed Jul 29 03:17:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of a stray line in the set_tls handler.
diff 6416:425703ea71c9 Wed Jul 29 03:09:00 EDT 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Ignore the "times" system call.
diff 6395:05f1d2cd7e9e Mon Jul 27 03:51:00 EDT 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Fix fstat/fstat64 structs to match EABI definitions.
diff 6393:1895318a1b26 Mon Jul 27 03:51:00 EDT 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Handle register indexed system calls.
diff 6236:9c0f2130478b Wed Jun 10 02:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params.
diff 6235:33adfb8af4c0 Wed Jun 10 02:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a memory_barrier function to the "comm page".
This function doesn't actually provide a memory barrier (I don't think they're
implemented) and instead just returns.
diff 6234:17e7ab512377 Wed Jun 10 02:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a cmpxchg implementation to the "comm page".
This implementation does what it's supposed to (I think), but it's not atomic
and doesn't have memory barriers like the kernel's version.
/gem5/src/arch/mips/
H A Dtlb.ccdiff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6038:4c21637acedd Sat Apr 18 10:42:00 EDT 2009 Korey Sewell <ksewell@umich.edu> mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS.
diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5894:8091ac99341a Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
diff 5891:73084c6bb183 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Replace the translate functions in the TLBs with translateAtomic.
H A Dtlb.hhdiff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5999:3cf8e71257e0 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: Fix all stats usages to deal with template fixes
diff 5894:8091ac99341a Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
diff 5891:73084c6bb183 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Replace the translate functions in the TLBs with translateAtomic.
diff 5877:9fe574944f31 Mon Feb 16 17:47:00 EST 2009 Lisa Hsu <hsul@eecs.umich.edu> sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
H A Disa.hhdiff 6806:45879b0e3240 Thu Dec 31 15:30:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.

The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.

This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
diff 6678:34191eea18c1 Sat Oct 17 04:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Fix compilation.
diff 6334:285b9886fee2 Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Fold the MiscRegFile all the way into the ISA object.
diff 6331:d947798df4a1 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
diff 6328:67dbc192f692 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Collapse ARM and MIPS regfile directories.
6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
H A Dsystem.ccdiff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
/gem5/src/base/
H A Dstatistics.ccdiff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
diff 6130:0fb959250892 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Move flags into info.hh and use base/flags.hh to manage the flags
diff 6128:fdfbd4c6e449 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Rename the info classes to hopefully make things a bit clearer
FooInfoBase became FooInfo
FooInfo became FooInfoProxy
diff 6026:45c8a91d1174 Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: disallow duplicate statistic names.
diff 6001:00251eb95de7 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: create an enable phase, and a prepare phase.
Enable more or less takes the place of check, but also allows stats to
do some other configuration. Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python code.
diff 6000:4f887be9e1b6 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: clean up how templates are used on the data side.
This basically works by taking advantage of the curiously recurring template
pattern in an intelligent way so as to reduce the number of lines of code
and hopefully make things a little bit clearer.
diff 5889:02e5bc7ca9ba Mon Feb 23 03:22:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: reorganize how parameters are stored and accessed.
diff 5887:6b312cafaa59 Mon Feb 23 03:22:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: get rid of the convoluted 'database' code.
Just use the stuff directly and things ought to be more clear
diff 5886:12431dc9a30a Mon Feb 23 03:22:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: Try to make the names of things more intuitive.
Basically, this means renaming several things called data to info, which
is information about the statistics. Things that are named data now are
actual data stored for the statistic.
/gem5/src/arch/alpha/
H A DSConscriptdiff 6330:786136379872 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Alpha: Pull the MiscRegFile fully into the ISA object.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6327:f6148086f997 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Alpha: Move reg_redir into its own files, and move some constants into regfile.hh.
diff 6321:c14676e17110 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
diff 6315:c7295a4826d5 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined floating point register file.
diff 6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
/gem5/src/arch/sparc/linux/
H A Dsyscalls.ccdiff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array.

When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
diff 6640:30d92d2b66a1 Wed Sep 16 01:36:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Syscalls: Implement sysinfo() syscall.
diff 6109:083d8a76b7a6 Tue Apr 21 11:17:00 EDT 2009 Daniel Sanchez <sanchezd@stanford.edu> Commit m5threads package.

This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call. The clone system call works
for Alpha, SPARC and x86, and multithreaded applications run
correctly in Alpha and SPARC.
diff 6075:1e1a874f9b17 Sun Apr 19 07:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SE mode: Make keeping track of the number of syscalls less hacky.
diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object.
diff 5877:9fe574944f31 Mon Feb 16 17:47:00 EST 2009 Lisa Hsu <hsul@eecs.umich.edu> sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
/gem5/src/base/stats/
H A Dtext.ccdiff 6212:64c3b989238c Wed May 13 10:18:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: fancy is a bad name
diff 6211:40e5a315bded Wed May 13 10:18:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: clean up the code for printing stats
diff 6130:0fb959250892 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Move flags into info.hh and use base/flags.hh to manage the flags
diff 6129:05405c5b8c16 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Shuffle around info stuff so it can be accessed separately
diff 6128:fdfbd4c6e449 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Rename the info classes to hopefully make things a bit clearer
FooInfoBase became FooInfo
FooInfo became FooInfoProxy
diff 6126:5f32f9e3c65a Wed Apr 22 13:25:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: remove simplescalar compatibility for printing
diff 6125:3bbbdd324a60 Wed Apr 22 09:44:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: fix initialization bug in distribution text output
diff 6004:97660425ff39 Sat Mar 07 17:30:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: cleanup text output stuff and fix mysql output
diff 5997:471090ec173e Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: stick the distribution's fancy parameter into the parameters structure.
diff 5889:02e5bc7ca9ba Mon Feb 23 03:22:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: reorganize how parameters are stored and accessed.
/gem5/src/mem/slicc/ast/
H A DTypeDeclAST.pydiff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DMachineAST.pydiff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/dev/alpha/
H A Dbackdoor.hhdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
/gem5/src/sim/
H A Ddebug.hhdiff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5882:5a047c3f3795 Mon Feb 23 14:48:00 EST 2009 Nathan Binkert <nate@binkert.org> debug: Move debug_break into src/base
/gem5/src/mem/ruby/common/
H A DHistogram.ccdiff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.

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