Searched hist:2009 (Results 226 - 250 of 951) sorted by relevance

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/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dscan_string.pydiff 6474:585faad1057f Fri Aug 07 00:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make scas compare its operands in the right order.
/gem5/src/base/
H A DCPA.py5952:c1ee8282291d Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> CPA: Add new object for gathering critical path annotations.
/gem5/src/mem/slicc/ast/
H A DAssignStatementAST.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DExprStatementAST.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DEnumDeclAST.pydiff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DTypeFieldEnumAST.pydiff 6690:4dc4e494e4d8 Mon Oct 26 20:06:00 EDT 2009 Brad Beckmann <Brad.Beckmann@amd.com> fixed error message generation bug in SLICC ast files
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/mem/slicc/symbols/
H A DState.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/mem/ruby/common/
H A DDataBlock.ccdiff 6288:083a6806dd96 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: apply some fixes that were overwritten by the recent ruby import.
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
H A DNetDest.hhdiff 6797:7bf0a839c237 Wed Nov 18 19:34:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> Resurrection of the CMP token protocol to GEM5
diff 6762:a22a47e60c21 Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby destruction fix.
diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/
H A Dmove.pydiff 6544:406ad51ece90 Mon Aug 17 21:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Move the MMX version of MOVD into the simd64 directory.
/gem5/src/arch/mips/
H A Didle_event.ccdiff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
/gem5/src/dev/x86/
H A Dsouth_bridge.ccdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
H A DI82094AA.pydiff 6803:c647872c6590 Sat Dec 19 04:50:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.
diff 6135:9327451a8e7a Sun Apr 26 05:04:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
diff 5859:2519ba935a5c Mon Feb 02 01:40:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add some missing default arguments.
diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dstack_operations.pydiff 6476:adbd07f1630d Fri Aug 07 13:12:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Don't truncate the immediate parameter for the ENTER instruction.
diff 6475:951199885fd8 Fri Aug 07 00:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Adjust the various sizes used for the enter and leave instructions.
diff 6344:b7104eda0795 Thu Jul 16 12:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a number of places where the wrong form of a microop was used.
diff 5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
/gem5/src/arch/x86/
H A Dintmessage.hhdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 6050:852ba59fa8d9 Sun Apr 19 06:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: The startup IPI delivery mode is not reserved.
diff 6046:8ac37d77fa74 Sun Apr 19 05:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the interrupt command register in the local APIC.
H A Dfaults.hhdiff 6049:595b5016f6d5 Sun Apr 19 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the STARTUP IPI.
diff 6048:65a321a3a691 Sun Apr 19 05:53:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INIT IPI.
diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6009:74bc713c71ce Sun Mar 08 00:34:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix compiler warnings in g++ 3.4
diff 5909:ecbd27e5d1f8 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a trace flag for tracing faults.
diff 5895:569e3b31a868 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
diff 5858:54f64fb1bd62 Sun Feb 01 20:09:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: All x86 fault classes now attempt to do something useful.
diff 5857:8cd8e1393990 Sun Feb 01 20:08:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the fault classes handle error codes better.
diff 5851:7bd73614dc1d Sun Feb 01 20:03:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Keep track of the vector for all exceptions/faults.
/gem5/src/arch/x86/linux/
H A Dprocess.hhdiff 6075:1e1a874f9b17 Sun Apr 19 07:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SE mode: Make keeping track of the number of syscalls less hacky.
diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object.
diff 5956:a49d9413a9e8 Fri Feb 27 12:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Distinguish the width of values on the stack between 32 and 64 bit processes.
diff 5955:d35d2b28df38 Fri Feb 27 12:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a class to support 32 bit x86 linux process.
/gem5/src/arch/alpha/
H A Dev5.hhdiff 6330:786136379872 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Alpha: Pull the MiscRegFile fully into the ISA object.
diff 6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/
H A Dgeneral_io.pydiff 5968:6f9f1438360a Fri Feb 27 12:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make instructions that use intseg preserve all 8 bytes of their addresses.
diff 5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
/gem5/src/base/stats/
H A Dtypes.hhdiff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5888:9775f70fbe66 Mon Feb 23 03:22:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: move the limits stuff into the types.hh file
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Djump.pydiff 6344:b7104eda0795 Thu Jul 16 12:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a number of places where the wrong form of a microop was used.
diff 6060:3d524dc980a8 Sun Apr 19 06:42:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement far jmp.
/gem5/src/mem/ruby/profiler/
H A DAccessTraceForAddress.ccdiff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/arm/
H A DArmNativeTrace.pydiff 6419:2192dac4ad82 Wed Jul 29 03:17:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make the ARM native tracer stop M5 if control diverges.
If the control flow of M5's executable and statetrace's target process get out
of sync even a little, there will be a LOT of output, very little of which
will be useful. There's also almost no hope for recovery. In those cases, we
might as well give up and not generate a huge, mostly worthless trace file.
6397:cb1d7c957f49 Mon Jul 27 03:51:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a native tracer.
/gem5/src/mem/ruby/slicc_interface/
H A DRubySlicc_ComponentMapping.hhdiff 6843:de4b394c6792 Tue Sep 15 21:39:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: added broadcast mechanism
diff 6785:bb675ba62c79 Wed Nov 18 19:34:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: returns the number of LLC needed for broadcast
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
diff 6468:26abdfe2d980 Wed Aug 05 00:05:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: made mapAddressToRange based off a bit count
diff 6467:5670eee2a866 Tue Aug 04 01:52:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate. They are:

1. Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2. DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/x86/isa/microops/
H A Dregop.isadiff 6742:a2a79fe9655d Wed Nov 11 17:49:00 EST 2009 Vince Weaver <vince@csl.cornell.edu> X86: add ULL to 1's being shifted in 64-bit values

Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems. On the perl makerand input this
caused some values to be negative that shouldn't have been.

The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
diff 6647:5a9fd91b66a3 Wed Sep 16 22:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Sign extend the immediate of wripi like the register version.
diff 6646:d9c23fff4f13 Wed Sep 16 22:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the imm8 member of immediate microops really 8 bits consistently.
diff 6482:e4b8ec60fd4b Sat Aug 08 20:23:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc.
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are filled with
zeros. They also both say that the CMOV instructions leave their destination
alone when their condition fails. Unfortunately, it seems that CMOV will zero
extend its destination register whether or not it was supposed to actually do
a move on both platforms. This seems to be the only case where this happens,
but it would be hard to say for sure.
diff 6479:b9ab1b56391b Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
diff 6464:2529aeaf1a1c Wed Aug 05 06:07:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make conditional moves zero extend their 32 bit destinations always.
diff 6463:fe6165923529 Wed Aug 05 06:07:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix condition code setting for signed multiplies with negative results.
diff 6462:209c3818a863 Wed Aug 05 06:06:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the check for negative operands for sign multiply more direct.
diff 6461:418145f4d7a6 Wed Aug 05 06:06:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make sure immediate values are truncated properly.
Register values will be "picked" which will assure they don't have junk beyond
the part we're using. Immediate values don't go through a similar process, so
we should truncate them explicitly.
diff 6456:57e6d35dde10 Wed Aug 05 06:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Handle rotate left with carry instructions that go all the way around or more.

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