Searched hist:2008 (Results 476 - 494 of 494) sorted by relevance
| /gem5/src/arch/x86/ | ||
| H A D | pagetable_walker.cc | diff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request |
| /gem5/src/sim/ | ||
| H A D | syscall_emul.hh | diff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5515:cff9ed9899c3 Thu Jul 24 19:31:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscall: Fix TTY emulation in fstat() user-mode simulation for fd 1 (stdout). The code didn't set S_IFCHR in the st_mode diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd. |
| /gem5/src/mem/ | ||
| H A D | page_table.hh | diff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. |
| /gem5/src/mem/cache/ | ||
| H A D | base.cc | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files. 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
| H A D | cache.cc | diff 5705:aea94955635b Thu Oct 23 16:11:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> remove the totally obsolete split cache |
| /gem5/src/base/ | ||
| H A D | SConscript | diff 5548:19d45fa7315c Fri Sep 19 12:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> atomicio: provide atomic read and write functions. These functions keep trying to read and write until all data has been transferred, or an error occurrs. In the case where an end of file hasn't been reached, but all of the bytes have not been read/written, try again. On EINTR, try again. |
| /gem5/src/cpu/o3/ | ||
| H A D | fetch_impl.hh | diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak. diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports. Force all non-default ports to provide a name and an owner in the constructor. |
| H A D | commit.hh | diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function |
| H A D | decode_impl.hh | diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
| H A D | lsq_unit_impl.hh | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function |
| H A D | rename_impl.hh | diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
| H A D | iew_impl.hh | diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
| /gem5/configs/example/ | ||
| H A D | fs.py | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. diff 5457:08bd3709d482 Fri Jun 13 01:09:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Scripts: Check for the appropriate build type as soon as possible. |
| /gem5/src/arch/sparc/ | ||
| H A D | faults.cc | diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases. |
| H A D | isa_traits.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
| /gem5/src/cpu/ | ||
| H A D | exetrace.cc | diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. |
| /gem5/util/term/ | ||
| H A D | term.c | diff 5580:6be5ac0eb1ea Wed Oct 01 16:37:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Cleanup m5term changes with Nate's comments. diff 5579:29cd33ac16cb Wed Oct 01 16:27:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Make m5term use select() so OS X is happy. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
| /gem5/src/arch/ | ||
| H A D | isa_parser.py | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
| /gem5/ | ||
| H A D | LICENSE | diff 5346:5e0130aed888 Mon Feb 11 00:35:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> Update copyright dates |
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