Searched hist:2008 (Results 301 - 325 of 494) sorted by relevance

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/gem5/src/arch/alpha/linux/
H A Dprocess.ccdiff 5759:6e65ac8a2c80 Fri Dec 05 00:09:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
diff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug.
Bogus calls to ChunkGenerator with negative size were triggering
a new assertion that was added there.
Also did a little renaming and cleanup in the process.
diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls.
readlink, umask, truncate, ftruncate, mkdir, and getcwd.
/gem5/src/arch/alpha/
H A Dstacktrace.ccdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory.
We should always refer to the specific ISA in that arch directory.
This is especially necessary if we're ever going to make it to the
point where we actually have heterogeneous systems.
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
/gem5/src/arch/x86/
H A Dcpuid.cc5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
/gem5/src/base/stats/
H A Dtext.ccdiff 5599:5bad83cddb8c Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> stats: use properly signed types for looping and comparison
diff 5598:345ef3bda3d2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Bring statistics code in line with the proper style.
diff 5581:5e1863e9afa2 Thu Oct 02 00:46:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Output: Verify output files are open after opening them.
diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
/gem5/src/arch/alpha/isa/
H A Ddecoder.isadiff 5780:50c9d48de3ca Wed Dec 17 12:51:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Make Alpha pseudo-insts available from SE mode.
diff 5741:323dac95e72c Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> pseudo inst: Add rpns (read processor nanoseconds) instruction.
This instruction basically returns the number of nanoseconds that the CPU
has been running.
diff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5505:90d6811d5ea6 Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> m5ops: clean up the m5ops stuff.
- insert warnings for deprecated m5ops
- reserve opcodes for Ali's stuff
- remove code for stuff that has been deprecated forever
- simplify m5op_alpha
H A Dmain.isadiff 5780:50c9d48de3ca Wed Dec 17 12:51:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Make Alpha pseudo-insts available from SE mode.
diff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
/gem5/src/cpu/o3/
H A Dthread_context.hhdiff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code.
diff 5595:6ebdae3f619b Thu Oct 09 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generalize the O3 CPU object so it isn't split out by ISA.
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5497:89a6483d7047 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Make the cached virtPort have a thread context so it can do everything that a newly created one can.
H A Dthread_context_impl.hhdiff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
H A Ddyn_inst.hhdiff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5596:cdc8893c649e Thu Oct 09 03:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
diff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5
H A Dcpu.ccdiff 5737:f43dbc09fad3 Mon Nov 10 14:51:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> O3CPU: Make the instcount debugging stuff per-cpu.
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5707:da86e00f87a0 Thu Oct 23 16:49:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
comments.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
/gem5/src/arch/sparc/
H A Dtlb.ccdiff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5646:0a488a147fb8 Sun Oct 12 11:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the get_vec function.
diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
diff 5555:07c10d7dd62d Tue Sep 23 23:38:00 EDT 2008 Nathan Binkert <nate@binkert.org> sparc: Fix style, create a helper function for translation.
The translate function simplifies code and removes some compiler
warnings in gcc 3.4
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
diff 5312:1dc4440797b6 Tue Jan 01 18:20:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> SPARC: Fix a bug where the TLB would match against the wrong entries.
H A Dua2005.ccdiff 5720:df9253dd6b4d Wed Nov 05 10:20:00 EST 2008 Nathan Binkert <nate@binkert.org> Fix a few more places where the context stuff wasn't changed
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5531:a5ff5e57fafd Mon Aug 11 17:47:00 EDT 2008 Nathan Binkert <nate@binkert.org> style
/gem5/src/arch/x86/isa/decoder/
H A Dtwo_byte_opcodes.isadiff 5683:e1a1d8bba254 Mon Oct 13 02:00:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the swapgs instruction.
diff 5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
diff 5422:f1f490fe77b0 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate.
diff 5409:0343cd06df4f Thu Jun 12 00:39:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add in some support for the tsc register.
diff 5359:8c6ff200e4c1 Tue Feb 26 23:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INVLPG instruction and the TIA microop.
diff 5332:0e25e0b6982c Tue Jan 22 00:10:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement and attach the BSR and BSF instructions.
diff 5331:8d8aaad0bc36 Mon Jan 21 16:27:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fill out group17 in the decoder.
/gem5/src/cpu/simple/
H A Dbase.hhdiff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5496:6899b894166f Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
diff 5348:7847a4bf9641 Thu Feb 14 16:14:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults.
H A Datomic.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5694:de7a82f58985 Mon Oct 13 02:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Explain why some code is commented out.
diff 5669:cbac62a59686 Sun Oct 12 22:32:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Don't fetch in the simple CPU if you're in the ROM.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5497:89a6483d7047 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Make the cached virtPort have a thread context so it can do everything that a newly created one can.
diff 5496:6899b894166f Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
diff 5487:f0ac4112e128 Wed Jun 18 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> AtomicSimpleCPU: Separate data stalls from instruction stalls.
Separate simulation of icache stalls and dat stalls.
diff 5408:703f1779cc89 Thu Jun 12 00:35:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Make the simple cpu trace data for loads/stores.
/gem5/src/mem/cache/tags/
H A Dfa_lru.hhdiff 5746:d7540fa81f1d Fri Nov 14 17:14:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> Cache: get rid of obsolete Tag methods.
I think readData() and writeData() were used for Erik's compression
work, but that code is gone, these aren't called anymore, and they
don't even really do what their names imply.
diff 5717:6ed48cba2217 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> decouple eviction from insertion in the cache.
diff 5716:ee56bb539212 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used.
diff 5706:2cc2387049bc Thu Oct 23 16:49:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> probe function no longer used anywhere.
diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files.
/gem5/src/mem/
H A Dport.ccdiff 5605:b194a80157e2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: Major API change for the Event and EventQueue structures.

Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object. In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event. Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when). To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers. The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function. Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
diff 5476:758c2413765a Mon Jun 16 00:34:00 EDT 2008 Nathan Binkert <nate@binkert.org> port: Clean up default port setup and port switchover code.
diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging.
H A Dbridge.ccdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5562:875cb7d09831 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> When nesting if statements, use braces to avoid ambiguous else clauses.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
diff 5476:758c2413765a Mon Jun 16 00:34:00 EDT 2008 Nathan Binkert <nate@binkert.org> port: Clean up default port setup and port switchover code.
diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging.
H A Dphysical.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5477:dc04d655315a Mon Jun 16 00:39:00 EDT 2008 Nathan Binkert <nate@binkert.org> physmem: Add a null option to physical memory so it doesn't store data.
diff 5399:e951ca2d56e2 Thu Apr 10 14:44:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> PhysicalMemory: Add parameter for variance in memory delay.
diff 5315:30997e988446 Wed Jan 02 16:46:00 EST 2008 Steve Reinhardt <stever@gmail.com> Additional comments and helper functions for PrintReq.
diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging.
/gem5/configs/common/
H A DFSConfig.pydiff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
diff 5644:2c54b5aa7769 Sat Oct 11 19:12:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add entries for the IO APIC to the MP table.
diff 5641:51b7b8cf8083 Sat Oct 11 18:14:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add an Intel MP table to the simulation.
diff 5638:dc073dc6358b Sat Oct 11 05:23:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Rename the PC device to Pc.
diff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects.
diff 5613:0d14611ee1bb Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System.
diff 5478:ca055528a3b3 Tue Jun 17 23:29:00 EDT 2008 Nathan Binkert <nate@binkert.org> Rename SimConsole to Terminal since it makes more sense
diff 5450:25e395a87745 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the e820 table manually or automatically configurable from python.
diff 5416:26aa7cf1be28 Thu Jun 12 00:46:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Force the kernel to use a certain loops per jiffy instead of calculating it.
diff 5412:771996f1d68e Thu Jun 12 00:45:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the amount of system memory match the hardcoded e820 info.
/gem5/src/cpu/
H A Dsimple_thread.hhdiff 5779:c0d731772342 Wed Dec 17 02:06:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> SPARC: Truncate syscall args and return values appropriately.
diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
H A Dstatic_inst.hhdiff 5677:c8479d55206c Sun Oct 12 23:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the MicroPC type 16 bit.
diff 5665:433182bf55c1 Sun Oct 12 19:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM.
diff 5597:e2983d751be4 Thu Oct 09 03:10:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 IMPL class so it isn't split out by ISA.
diff 5596:cdc8893c649e Thu Oct 09 03:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5
H A Dbase.ccdiff 5718:323cfbfec1a4 Wed Nov 05 15:30:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system. To make them match,
here is a little change.
diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in
SE. Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
diff 5646:0a488a147fb8 Sun Oct 12 11:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the get_vec function.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
/gem5/src/sim/
H A Dpseudo_inst.ccdiff 5780:50c9d48de3ca Wed Dec 17 12:51:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Make Alpha pseudo-insts available from SE mode.
diff 5741:323dac95e72c Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> pseudo inst: Add rpns (read processor nanoseconds) instruction.
This instruction basically returns the number of nanoseconds that the CPU
has been running.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5505:90d6811d5ea6 Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> m5ops: clean up the m5ops stuff.
- insert warnings for deprecated m5ops
- reserve opcodes for Ali's stuff
- remove code for stuff that has been deprecated forever
- simplify m5op_alpha
diff 5504:288b54c2fd8d Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: fix indentation and formatting of the pseudo insts.
/gem5/src/
H A DSConscriptdiff 5742:828a8296270e Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> SCons: Allow top level directory of EXTRAS able to contain SConscripts.
The current EXTRAS will fail if the top level directory pointed to by EXTRAS
has a SConscript file in it. We allow this by including the directory name
of the EXTRA in the build directory which prevents a clash between
src/SConscript and extra/SConscript. Maintain compatibility with older uses
of EXTRAS by adding a -I for each top level extra directory.
diff 5623:11a1079070b6 Sat Oct 11 00:45:00 EDT 2008 Nathan Binkert <nate@binkert.org> swig: Add in a %rename to allow the same name to appear in multiple namespaces.
diff 5610:0e1e9c186769 Fri Oct 10 01:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> SimObjects: Clean up handling of C++ namespaces.
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
diff 5604:7c58fc1ec5dc Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> pdb: Try to make pdb work better.
I've done a few things here. First, I invoke the script a little bit
differently so that pdb doesn't get confused. Second, I've stored the
actual filename in the module's __file__ so that pdb can find the
source file on your machine.
diff 5601:1acb7016d0e4 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> SCons: add code to provide a libm5 shared library.
Targets look like libm5_debug.so. This target can be dynamically
linked into another C++ program and provide just about all of the M5
features. Additionally, this library is a standalone module that can
be imported into python with an "import libm5_debug" type command
line.
diff 5584:e08e65fd0f76 Thu Oct 02 14:27:00 EDT 2008 Nathan Binkert <nate@binkert.org> unittest: Add unit tests to the scons framework.
Also fix the unit tests so they actually compile correctly.
diff 5559:660fa7b652f5 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> scons: disable several gcc warnings for swig autogenerated wrapper code.
diff 5554:e6fabe023fe1 Mon Sep 22 11:25:00 EDT 2008 Nathan Binkert <nate@binkert.org> scons: Separate swig environment so we can have different flags.
Swig code isn't quite perfect, so let's not turn on all of the warnings.
diff 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5.

This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack. This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name. Additionally, a new Importer
was needed to allow python to get at the embedded python code.

Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things. Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.

The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
diff 5518:70caf53d9d7c Sat Aug 02 23:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> kill unused code

Completed in 525 milliseconds

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