Searched hist:2008 (Results 226 - 250 of 494) sorted by relevance

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/gem5/src/python/
H A Dimporter.py5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5.

This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack. This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name. Additionally, a new Importer
was needed to allow python to get at the embedded python code.

Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things. Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.

The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
/gem5/src/arch/alpha/
H A Dsystem.ccdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5566:3440c9ad49b4 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
H A Dvtophys.hhdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
H A Dtlb.ccdiff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request
diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5566:3440c9ad49b4 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5532:d8ab33f5ff9a Wed Aug 13 16:29:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Return an UnimpFault for an ITB translation of an uncachable address. We don't support fetching from uncached addresses in Alpha and it means that a speculative fetch can clobber device registers.
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
H A Dutility.hhdiff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5552:9437b71c6460 Mon Sep 22 11:21:00 EDT 2008 Nathan Binkert <nate@binkert.org> style
diff 5549:ed9b39dce0aa Fri Sep 19 12:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> We're using the static keyword improperly in some cases.
H A Dfaults.ccdiff 5764:f07df23e1fc8 Sat Dec 06 17:18:00 EST 2008 Nathan Binkert <nate@binkert.org> flags: Change naming of functions to be clearer
diff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request
diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5566:3440c9ad49b4 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
/gem5/src/cpu/
H A Dsimple_thread.ccdiff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
H A Dquiesce_event.ccdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
/gem5/
H A DREADMEdiff 5587:664630aaf316 Tue Oct 07 00:53:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Update the README and RELEASE_NOTES files to prepare for beta 6.
diff 5356:16f57bce72d6 Tue Feb 26 17:28:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> Update make release, README, and RELEASE_NOTES for b5
/gem5/src/dev/
H A Dmc146818.ccdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
5392:c3a45fac35f8 Tue Mar 25 02:15:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.
/gem5/src/arch/sparc/
H A Dpagetable.hhdiff 5616:05fd71ca96db Fri Oct 10 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> misc: remove #include <cassert> from misc.hh since not everyone needs it.
diff 5555:07c10d7dd62d Tue Sep 23 23:38:00 EDT 2008 Nathan Binkert <nate@binkert.org> sparc: Fix style, create a helper function for translation.
The translate function simplifies code and removes some compiler
warnings in gcc 3.4
/gem5/src/base/
H A Dbitunion.hhdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5442:0552284c5b8b Thu Jun 12 00:54:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> BitUnion: Take out namespace declaration so bitunions can be declared inside classes.
/gem5/src/dev/alpha/
H A Dbackdoor.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
5480:b9460d7f74f0 Tue Jun 17 23:36:00 EDT 2008 Nathan Binkert <nate@binkert.org> rename AlphaConsole to AlphaBackdoor
/gem5/src/arch/x86/linux/
H A Dlinux.hhdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5407:c121bb9e86eb Wed Jun 11 10:54:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> X86: Fix building on *BSD hosts
/gem5/src/dev/sparc/
H A Diob.ccdiff 5719:c9056088f151 Wed Nov 05 16:19:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Fix SPARC_FS compile
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
/gem5/src/mem/cache/
H A DSConscriptdiff 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.
diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging.
/gem5/src/mem/cache/tags/
H A DSConscriptdiff 5705:aea94955635b Thu Oct 23 16:11:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> remove the totally obsolete split cache
diff 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.
/gem5/src/sim/
H A Dvptr.hhdiff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5498:2af99511ded4 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Change everything to use the cached virtPort rather than created their own each time.
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
/gem5/src/arch/x86/isa/microops/
H A Ddebug.isadiff 5591:b05a5c5452e0 Thu Oct 09 03:05:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix the debugging microops. The debug functions can't handle a string object format.
5425:4226f6c2d03c Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops which panic, fatal, warn, and warn_once.
/gem5/src/arch/x86/isa/
H A Doperands.isadiff 5682:6f1cab082ba7 Mon Oct 13 01:55:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add wrval/rdval microops for reading significant miscregs.
diff 5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
diff 5429:52dbcf7f7328 Thu Jun 12 00:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Keep handy values like the operating mode in one register.
diff 5428:5a27fea50fee Thu Jun 12 00:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change what the microop chks does.
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
diff 5426:0bdcc60ccc45 Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops and supporting code to manipulate the whole rflags register.
diff 5409:0343cd06df4f Thu Jun 12 00:39:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add in some support for the tsc register.
/gem5/src/mem/
H A Dtport.ccdiff 5740:983b71bfc1bd Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> Clean up the SimpleTimingPort class a little bit.
Move the constructor into the .cc file and get rid of the typedef for
SendEvent.
diff 5693:4bf6f614871b Mon Oct 13 02:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of some commented out code.
diff 5650:d2782c951841 Sun Oct 12 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Create a message port for sending messages as apposed to reading/writing a memory range.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5459:b84a60dbf862 Fri Jun 13 01:33:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Get rid of bogus bus assertion.
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
diff 5387:3323952c3bb4 Mon Mar 24 01:08:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Delete the Request for a no-response Packet
when the Packet is deleted, since the requester
can't possibly do it.
H A Drequest.hhdiff 5764:f07df23e1fc8 Sat Dec 06 17:18:00 EST 2008 Nathan Binkert <nate@binkert.org> flags: Change naming of functions to be clearer
diff 5745:6b0f8306704b Fri Nov 14 07:55:00 EST 2008 Nathan Binkert <nate@binkert.org> Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out. I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.
diff 5744:342cbc20a188 Fri Nov 14 02:30:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Refactor read/write in the simple timing CPU.
diff 5735:a88e8e7dec75 Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> style: clean up the Packet stuff
diff 5731:453f320129a1 Mon Nov 10 17:11:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: Assert that requests have non-negative size.
Would have saved me much debugging time if these
had been in there previously.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5607:eb9b92bf37ec Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> mem: Add a method for setting the time on a packet.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5466:a1981d557252 Sat Jun 14 22:39:00 EDT 2008 Nathan Binkert <nate@binkert.org> MemReq: Add option to reset the time on a request.
/gem5/configs/common/
H A DSimulation.pydiff 5378:7c058e69f257 Sat Mar 15 22:20:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist
diff 5371:dce5a8655829 Fri Feb 29 01:49:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Error out if -s is used without --caches (instead of saying you must specify a
CPU).
diff 5370:b16ec4d7e77c Fri Feb 29 01:23:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> Configs: Make sure options don't conflict
diff 5369:9358355117b0 Thu Feb 28 20:39:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> Configs: Fix some bugs we introduced in the simpoints code
diff 5361:e379019a1abd Wed Feb 27 00:35:00 EST 2008 Rick Strong <rstrong@cs.ucsd.edu> Configs: Make using Simpoints easier with some config files that support them easily
diff 5353:487d6f3291d7 Fri Feb 22 17:48:00 EST 2008 Vilas Sridharan <vilas.sridharan@gmail.com> add instruction count fast forwaing and max instruction options
diff 5347:f15b21a5bd2e Thu Feb 14 16:13:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.
/gem5/tests/
H A DSConscriptdiff 5773:7434b2271b0c Mon Dec 08 10:16:00 EST 2008 Nathan Binkert <nate@binkert.org> output: Change default output directory and files and update tests.
diff 5721:11e6f4fa85c3 Wed Nov 05 18:10:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> new mp eio test
diff 5703:7478bc206949 Mon Oct 20 19:00:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
diff 5526:2764c7769ee3 Mon Aug 04 01:01:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Minor fix for test/SConscript... forgot to 'qref' before 'qdel', argh.
diff 5525:abb8846b2e62 Mon Aug 04 00:48:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Make test/SConscript use new redirection options.
/gem5/src/base/loader/
H A Delf_object.ccdiff 5759:6e65ac8a2c80 Fri Dec 05 00:09:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
diff 5616:05fd71ca96db Fri Oct 10 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> misc: remove #include <cassert> from misc.hh since not everyone needs it.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5383:51dc65015ca9 Thu Mar 20 02:10:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> MIPS: Check endianness of binaries in SE mode.
diff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5

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