Searched hist:2008 (Results 151 - 175 of 494) sorted by relevance

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/gem5/src/arch/x86/isa/microops/
H A Dbase.isadiff 5692:0d6addcde185 Mon Oct 13 02:29:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Set the delayed commit flag in x86 microops appropriately.
diff 5667:78b94954f66a Sun Oct 12 20:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a handy way to access labels from the ROM in microcode.
diff 5666:e7925fa8f0d6 Sun Oct 12 20:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make X86's microcode ROM actually do something.
H A Dregop.isadiff 5682:6f1cab082ba7 Mon Oct 13 01:55:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add wrval/rdval microops for reading significant miscregs.
diff 5679:0b7855e2b731 Mon Oct 13 01:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make sure register microops set fault rather than returning one.
diff 5678:9af6981bb086 Mon Oct 13 01:16:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors.
diff 5675:7828ee363019 Sun Oct 12 23:38:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the chks check of interrupt gate target code segments.
diff 5674:4a4f20dfbc60 Sun Oct 12 23:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add a check type for interrupt gates.
diff 5673:57be483cea36 Sun Oct 12 23:29:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix chks checking the submode for stack segments.
diff 5672:f332946e12b2 Sun Oct 12 23:25:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Let segment manipulation microops be conditional.
diff 5670:1df7cdfc4aa6 Sun Oct 12 23:07:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix the rdbase microop
diff 5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
diff 5433:1b0b8e9ba6a9 Thu Jun 12 00:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change how segment loading is performed.
/gem5/src/python/m5/
H A Devent.pydiff 5738:6ea35903c420 Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> python: Fix the reference counting for python events placed on the eventq.
We need to add a reference when an object is put on the C++ queue, and remove
a reference when the object is removed from the queue. This was not happening
before and caused a memory problem.
diff 5696:be57a48fb100 Tue Oct 14 12:34:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: make python events actually work
diff 5605:b194a80157e2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: Major API change for the Event and EventQueue structures.

Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object. In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event. Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when). To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers. The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function. Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
/gem5/src/mem/
H A Dmem_object.hhdiff 5530:bbfff6d0c42c Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Get rid of the remnants of the old style parameter configuration stuff.
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
/gem5/src/dev/x86/
H A DSouthBridge.pydiff 5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
diff 5643:2b1611137af4 Sat Oct 11 19:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create an IO APIC device.
5637:3d2451ebad92 Sat Oct 11 05:21:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge directory.
H A DI8254.py5636:27a9526eea1f Sat Oct 11 05:16:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices.
/gem5/src/arch/x86/bios/
H A De820.hh5450:25e395a87745 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the e820 table manually or automatically configurable from python.
H A Dintelmp.hh5625:ea7d3676ac8d Sat Oct 11 02:39:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create SimObjects in python and C++ to represent the Intel MP tables.
/gem5/src/arch/x86/isa/insts/
H A Dromutil.py5680:39ae093fb4eb Mon Oct 13 01:42:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement entering an interrupt in microcode.
/gem5/src/arch/sparc/linux/
H A Dlinux.ccdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
/gem5/src/arch/alpha/
H A Dpagetable.ccdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
/gem5/src/base/
H A Dstr.ccdiff 5547:747034106af4 Fri Sep 19 12:11:00 EDT 2008 Nathan Binkert <nate@binkert.org> Use C++ limits where applicable for portability
H A Dinet.hhdiff 5761:94d56a48d7e3 Fri Dec 05 13:58:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> INet: Allow updating on id, len, seq, and flag field for TCP segment offload
diff 5484:dc6a459769a1 Wed Jun 18 01:14:00 EDT 2008 Nathan Binkert <nate@binkert.org> inet: initialization fixes.
Make sure variables are properly initialized and also make sure that
truth testing works properly.
H A Doutput.hhdiff 5749:7015e400bd1d Sat Nov 15 23:42:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> Output: Include gzstream package to allow automatically-gzipped output
The gzstream package provides an ostream-interface for writing gzipped files.
The package comes from:
http://www.cs.unc.edu/Research/compgeom/gzstream/
And is distributed under the LGPL license. Both the license and version
information has been preservered, though all other files in the package have
been purged. Minor modifications to the code have been made. The output module
detects when a filename ends in .gz and constructs an ogzstream object instead
of an ofstream object. This works for both the create(...) and find(...)
commands. Additionally, since gzstream objects needs to be closed to ensure
proper file termination, I have the output deconstructor deleting all ostream's
that it manages on behalf of find(...). At the moment, the only output file
that I know this functionality works for is stats, i.e. by specifying
"--stats-file=m5stats.txt.gz" on the command line.
diff 5402:05c388940eb6 Thu May 15 19:10:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Make sure that output files are always checked success before they're used.
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dcall.pydiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
/gem5/src/kern/
H A Doperatingsystem.hhdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
/gem5/
H A D.hgignorediff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5
/gem5/src/arch/mips/
H A Ddsp.hhdiff 5558:cb98f0fcc6c6 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: These files didn't even come close to following the M5 style guide.
H A Dlocked_mem.hhdiff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5596:cdc8893c649e Thu Oct 09 03:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
/gem5/ext/libelf/
H A DSConscriptdiff 5765:fdfd6e4aad66 Sat Dec 06 17:18:00 EST 2008 Nathan Binkert <nate@binkert.org> scons: only use -Wno-pointer-sign with gcc >= 4.3
diff 5711:93eb7f618517 Tue Oct 28 21:13:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Libelf: Append options to CCFLAGS for warning free libelf compile instead of deleting CCFLAGS. Should fix 64bit OS X compile problem.
diff 5601:1acb7016d0e4 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> SCons: add code to provide a libm5 shared library.
Targets look like libm5_debug.so. This target can be dynamically
linked into another C++ program and provide just about all of the M5
features. Additionally, this library is a standalone module that can
be imported into python with an "import libm5_debug" type command
line.
diff 5397:58e5b68f7095 Mon Apr 07 23:40:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: Make BATCH options global sticky so libelf is built appropriately.
/gem5/src/arch/x86/isa/insts/system/
H A Dsegmentation.pydiff 5683:e1a1d8bba254 Mon Oct 13 02:00:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the swapgs instruction.
/gem5/src/cpu/simple/
H A DSConscriptdiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
/gem5/src/dev/mips/
H A DMalta.pydiff 5481:5afd4f01c824 Tue Jun 17 23:39:00 EDT 2008 Nathan Binkert <nate@binkert.org> rename MipsConsole to MipsBackdoor
/gem5/src/mem/cache/prefetch/
H A Dstride.hhdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files.
5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.
/gem5/src/python/m5/util/
H A Dmultidict.py5467:6d9df90d70d7 Sat Jun 14 23:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> python: Move various utility classes into a new m5.util package so
they're all in the same place. This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication. Lots of improvements to the utility as well.

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