History log of /gem5/.hgignore
Revision Date Author Comments
# 11864:7ba0f5d4ad70 21-Feb-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Add dtb files to the ignore list for git and mercurial

Change-Id: Ifb135c60e050c55769914e853b07a387c06e4007
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>


# 11206:2375b33bddc6 13-Nov-2015 Anthony Gutierrez <atgutier@umich.edu>

misc: ignore object files and static libs in util/m5


# 10235:0db28826e333 04-Jun-2014 Yasuko Eckert <yasuko.eckert@amd.com>

ext: Add a McPAT regression tester
Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko
Eckert modified them to reflect the new McPAT interface and other changes
the previous patch made.


# 10066:06a33d872798 18-Feb-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.


# 7514:b28e7286990c 27-Jul-2010 Steve Reinhardt <steve.reinhardt@amd.com>

.hgignore: added src/doxygen


# 6792:64b815f299c0 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

m5: Added the default m5out directory to the hg ignore list


# 5335:69d45f5f21a2 05-Feb-2008 Stephen Hines <hines@cs.fsu.edu>

Add base ARM code to M5


# 4939:80c00f93a418 03-Aug-2007 Steve Reinhardt <stever@gmail.com>

Add cscope files to .hgignore.


# 4677:50d1e67c44ec 14-Jul-2007 Nathan Binkert <nate@binkert.org>

ignore stuff that we don't want to see in the status