Searched defs:override (Results 276 - 300 of 324) sorted by relevance

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/gem5/src/mem/cache/compressors/
H A Dcpack.hh183 const uint64_t* data, Cycles& comp_lat, Cycles& decomp_lat) override; member in class:CPack
191 void decompress(const CompressionData* comp_data, uint64_t* data) override; member in class:CPack
210 void regStats() override; member in class:CPack
/gem5/src/cpu/kvm/
H A Dbase.hh84 void init() override; member in class:BaseKvmCPU
85 void startup() override; member in class:BaseKvmCPU
86 void regStats() override; member in class:BaseKvmCPU
88 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; member in class:BaseKvmCPU
89 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; member in class:BaseKvmCPU
91 DrainState drain() override; member in class:BaseKvmCPU
92 void drainResume() override; member in class:BaseKvmCPU
93 void notifyFork() override; member in class:BaseKvmCPU
95 void switchOut() override; member in class:BaseKvmCPU
96 void takeOverFrom(BaseCPU *cpu) override; member in class:BaseKvmCPU
98 void verifyMemoryMode() const override; member in class:BaseKvmCPU
103 void wakeup(ThreadID tid = 0) override; member in class:BaseKvmCPU
104 void activateContext(ThreadID thread_num) override; member in class:BaseKvmCPU
105 void suspendContext(ThreadID thread_num) override; member in class:BaseKvmCPU
107 void haltContext(ThreadID thread_num) override; member in class:BaseKvmCPU
110 ThreadContext *getContext(int tn) override; member in class:BaseKvmCPU
112 Counter totalInsts() const override; member in class:BaseKvmCPU
113 Counter totalOps() const override; member in class:BaseKvmCPU
606 bool recvTimingResp(PacketPtr pkt) override; member in class:BaseKvmCPU::KVMCpuPort
608 void recvReqRetry() override; member in class:BaseKvmCPU::KVMCpuPort
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/gem5/src/mem/ruby/system/
H A DRubyPort.hh149 void init() override; member in class:RubyPort
152 PortID idx=InvalidPortID) override; member in class:RubyPort
165 DrainState drain() override; member in class:RubyPort
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.hh249 PortID idx=InvalidPortID) override; member in class:BaseTrafficGen
251 void init() override; member in class:BaseTrafficGen
253 DrainState drain() override; member in class:BaseTrafficGen
255 void serialize(CheckpointOut &cp) const override; member in class:BaseTrafficGen
256 void unserialize(CheckpointIn &cp) override; member in class:BaseTrafficGen
/gem5/src/mem/ruby/network/
H A DMessageBuffer.hh131 void regStats() override; member in class:MessageBuffer
/gem5/src/arch/arm/insts/
H A Dmem64.hh62 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::SysDC64
143 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryImm64
159 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryDImm64
175 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryDImmEx64
188 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryPreIndex64
201 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryPostIndex64
220 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryReg64
232 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryRaw64
247 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryEx64
261 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryLiteral64
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H A Dmem.hh112 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::RfeOp
153 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::SrsOp
H A Dmacromem.hh267 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroSetPCCPSR
286 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroIntMov
306 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroIntImmOp
323 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroIntImmXOp
342 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroIntOp
362 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroIntRegXOp
402 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroMemOp
423 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MicroMemPairOp
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/gem5/src/dev/arm/
H A Dsmmu_v3.hh173 virtual void init() override; member in class:SMMUv3
174 virtual void regStats() override; member in class:SMMUv3
187 DrainState drain() override; member in class:SMMUv3
188 void serialize(CheckpointOut &cp) const override; member in class:SMMUv3
189 void unserialize(CheckpointIn &cp) override; member in class:SMMUv3
192 PortID id = InvalidPortID) override; member in class:SMMUv3
H A Drv_ctrl.hh175 Tick read(PacketPtr pkt) override; member in class:RealViewCtrl
182 Tick write(PacketPtr pkt) override; member in class:RealViewCtrl
184 void serialize(CheckpointOut &cp) const override; member in class:RealViewCtrl
185 void unserialize(CheckpointIn &cp) override; member in class:RealViewCtrl
210 void startup() override; member in class:RealViewOsc
212 void serialize(CheckpointOut &cp) const override; member in class:RealViewOsc
213 void unserialize(CheckpointIn &cp) override; member in class:RealViewOsc
216 uint32_t read() const override; member in class:RealViewOsc
217 void write(uint32_t freq) override; member in class:RealViewOsc
242 uint32_t read() const override; member in class:RealViewTemperatureSensor
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H A Dgic_v2.hh201 void serialize(CheckpointOut &cp) const override; member in struct:GicV2::BankedRegs
202 void unserialize(CheckpointIn &cp) override; member in struct:GicV2::BankedRegs
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H A Dsmmu_v3_caches.hh320 void regStats(const std::string &name) override; member in class:WalkCache
H A Dgic_v3_redistributor.hh221 void serialize(CheckpointOut & cp) const override; member in class:Gicv3Redistributor
222 void unserialize(CheckpointIn & cp) override; member in class:Gicv3Redistributor
H A Dgic_v3_distributor.hh232 void serialize(CheckpointOut & cp) const override; member in class:Gicv3Distributor
233 void unserialize(CheckpointIn & cp) override; member in class:Gicv3Distributor
/gem5/src/dev/x86/
H A Di8042.hh142 AddrRangeList getAddrRanges() const override; member in class:X86ISA::I8042
144 Tick read(PacketPtr pkt) override; member in class:X86ISA::I8042
146 Tick write(PacketPtr pkt) override; member in class:X86ISA::I8042
148 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::I8042
149 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::I8042
/gem5/src/arch/x86/
H A Dinterrupts.hh200 void init() override; member in class:X86ISA::Interrupts
205 Tick read(PacketPtr pkt) override; member in class:X86ISA::Interrupts
206 Tick write(PacketPtr pkt) override; member in class:X86ISA::Interrupts
208 bool recvResponse(PacketPtr pkt) override; member in class:X86ISA::Interrupts
219 AddrRangeList getAddrRanges() const override; member in class:X86ISA::Interrupts
275 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::Interrupts
276 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::Interrupts
/gem5/src/gpu-compute/
H A Dtlb_coalescer.hh146 void regStats() override; member in class:TLBCoalescer
215 PortID idx=InvalidPortID) override; member in class:TLBCoalescer
/gem5/src/cpu/simple/
H A Dtiming.hh58 void init() override; member in class:TimingSimpleCPU
274 DrainState drain() override; member in class:TimingSimpleCPU
275 void drainResume() override; member in class:TimingSimpleCPU
277 void switchOut() override; member in class:TimingSimpleCPU
278 void takeOverFrom(BaseCPU *oldCPU) override; member in class:TimingSimpleCPU
280 void verifyMemoryMode() const override; member in class:TimingSimpleCPU
282 void activateContext(ThreadID thread_num) override; member in class:TimingSimpleCPU
283 void suspendContext(ThreadID thread_num) override; member in class:TimingSimpleCPU
288 override; member in class:TimingSimpleCPU
293 override; member in class:TimingSimpleCPU
296 AtomicOpFunctorPtr amo_op) override; member in class:TimingSimpleCPU
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/gem5/src/arch/hsail/insts/
H A Dmem.hh399 void generateDisassembly() override; member in class:HsailISA::LdInst
698 void execute(GPUDynInstPtr gpuDynInst) override; member in class:HsailISA::LdInst
960 void generateDisassembly() override; member in class:HsailISA::StInst
1173 void execute(GPUDynInstPtr gpuDynInst) override; member in class:HsailISA::StInst
1464 void generateDisassembly() override; member in class:HsailISA::AtomicInst
1559 void execute(GPUDynInstPtr gpuDynInst) override; member in class:HsailISA::AtomicInst
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/gem5/src/arch/arm/
H A Dpmu.hh108 void serialize(CheckpointOut &cp) const override; member in class:ArmISA::PMU
109 void unserialize(CheckpointIn &cp) override; member in class:ArmISA::PMU
111 void drainResume() override; member in class:ArmISA::PMU
113 void regProbeListeners() override; member in class:ArmISA::PMU
116 void setThreadContext(ThreadContext *tc) override; member in class:ArmISA::PMU
124 void setMiscReg(int misc_reg, RegVal val) override; member in class:ArmISA::PMU
131 RegVal readMiscReg(int misc_reg) override; member in class:ArmISA::PMU
382 void enable() override; member in struct:ArmISA::PMU::RegularEvent
384 void disable() override; member in struct:ArmISA::PMU::RegularEvent
419 void serialize(CheckpointOut &cp) const override; member in struct:ArmISA::PMU::CounterState
420 void unserialize(CheckpointIn &cp) override; member in struct:ArmISA::PMU::CounterState
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/gem5/src/arch/sparc/
H A Disa.hh171 void serialize(CheckpointOut &cp) const override; member in class:SparcISA::ISA
172 void unserialize(CheckpointIn &cp) override; member in class:SparcISA::ISA
/gem5/src/dev/virtio/
H A Dbase.hh324 void serialize(CheckpointOut &cp) const override; member in class:VirtQueue
325 void unserialize(CheckpointIn &cp) override; member in class:VirtQueue
600 void serialize(CheckpointOut &cp) const override; member in class:VirtIODeviceBase
601 void unserialize(CheckpointIn &cp) override; member in class:VirtIODeviceBase
/gem5/src/cpu/pred/
H A Dstatistical_corrector.hh262 void init() override; member in class:StatisticalCorrector
263 void regStats() override; member in class:StatisticalCorrector
/gem5/src/mem/
H A Dcomm_monitor.hh82 void init() override; member in class:CommMonitor
83 void startup() override; member in class:CommMonitor
84 void regProbePoints() override; member in class:CommMonitor
88 PortID idx=InvalidPortID) override; member in class:CommMonitor
/gem5/src/cpu/checker/
H A Dcpu.hh96 void init() override; member in class:CheckerCPU
177 void serialize(CheckpointOut &cp) const override; member in class:CheckerCPU
178 void unserialize(CheckpointIn &cp) override; member in class:CheckerCPU
560 override; member in class:CheckerCPU
565 override; member in class:CheckerCPU
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