1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
44#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
45
46#include "base/addr_range.hh"
47#include "dev/arm/gic_v3.hh"
48#include "sim/serialize.hh"
49
50class Gicv3Distributor : public Serializable
51{
52  private:
53
54    friend class Gicv3Redistributor;
55    friend class Gicv3CPUInterface;
56    friend class Gicv3Its;
57
58  protected:
59
60    Gicv3 * gic;
61    const uint32_t itLines;
62
63    enum {
64        // Control Register
65        GICD_CTLR  = 0x0000,
66        // Interrupt Controller Type Register
67        GICD_TYPER = 0x0004,
68        // Implementer Identification Register
69        GICD_IIDR = 0x0008,
70        // Error Reporting Status Register
71        GICD_STATUSR = 0x0010,
72        // Set Non-secure SPI Pending Register
73        GICD_SETSPI_NSR = 0x0040,
74        // Clear Non-secure SPI Pending Register
75        GICD_CLRSPI_NSR = 0x0048,
76        // Set Secure SPI Pending Register
77        GICD_SETSPI_SR = 0x0050,
78        // Clear Secure SPI Pending Register
79        GICD_CLRSPI_SR = 0x0058,
80        // Software Generated Interrupt Register
81        GICD_SGIR = 0x0f00,
82        // Peripheral ID0 Register
83        GICD_PIDR0 = 0xffe0,
84        // Peripheral ID1 Register
85        GICD_PIDR1 = 0xffe4,
86        // Peripheral ID2 Register
87        GICD_PIDR2 = 0xffe8,
88        // Peripheral ID3 Register
89        GICD_PIDR3 = 0xffec,
90        // Peripheral ID4 Register
91        GICD_PIDR4 = 0xffd0,
92        // Peripheral ID5 Register
93        GICD_PIDR5 = 0xffd4,
94        // Peripheral ID6 Register
95        GICD_PIDR6 = 0xffd8,
96        // Peripheral ID7 Register
97        GICD_PIDR7 = 0xffdc,
98    };
99
100    // Interrupt Group Registers
101    static const AddrRange GICD_IGROUPR;
102    // Interrupt Set-Enable Registers
103    static const AddrRange GICD_ISENABLER;
104    // Interrupt Clear-Enable Registers
105    static const AddrRange GICD_ICENABLER;
106    // Interrupt Set-Pending Registers
107    static const AddrRange GICD_ISPENDR;
108    // Interrupt Clear-Pending Registers
109    static const AddrRange GICD_ICPENDR;
110    // Interrupt Set-Active Registers
111    static const AddrRange GICD_ISACTIVER;
112    // Interrupt Clear-Active Registers
113    static const AddrRange GICD_ICACTIVER;
114    // Interrupt Priority Registers
115    static const AddrRange GICD_IPRIORITYR;
116    // Interrupt Processor Targets Registers
117    static const AddrRange GICD_ITARGETSR; // GICv2 legacy
118    // Interrupt Configuration Registers
119    static const AddrRange GICD_ICFGR;
120    // Interrupt Group Modifier Registers
121    static const AddrRange GICD_IGRPMODR;
122    // Non-secure Access Control Registers
123    static const AddrRange GICD_NSACR;
124    // SGI Clear-Pending Registers
125    static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
126    // SGI Set-Pending Registers
127    static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
128    // Interrupt Routing Registers
129    static const AddrRange GICD_IROUTER;
130
131    BitUnion64(IROUTER)
132        Bitfield<63, 40> res0_1;
133        Bitfield<39, 32> Aff3;
134        Bitfield<31>     IRM;
135        Bitfield<30, 24> res0_2;
136        Bitfield<23, 16> Aff2;
137        Bitfield<15, 8>  Aff1;
138        Bitfield<7, 0>   Aff0;
139    EndBitUnion(IROUTER)
140
141    static const uint32_t GICD_CTLR_ENABLEGRP0   = 1 << 0;
142    static const uint32_t GICD_CTLR_ENABLEGRP1   = 1 << 0;
143    static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
144    static const uint32_t GICD_CTLR_ENABLEGRP1A  = 1 << 1;
145    static const uint32_t GICD_CTLR_ENABLEGRP1S  = 1 << 2;
146    static const uint32_t GICD_CTLR_DS           = 1 << 6;
147
148    bool ARE;
149    bool DS;
150    bool EnableGrp1S;
151    bool EnableGrp1NS;
152    bool EnableGrp0;
153    std::vector <uint8_t> irqGroup;
154    std::vector <bool> irqEnabled;
155    std::vector <bool> irqPending;
156    std::vector <bool> irqActive;
157    std::vector <uint8_t> irqPriority;
158    std::vector <Gicv3::IntTriggerType> irqConfig;
159    std::vector <uint8_t> irqGrpmod;
160    std::vector <uint8_t> irqNsacr;
161    std::vector <IROUTER> irqAffinityRouting;
162
163    uint32_t gicdTyper;
164    uint32_t gicdPidr0;
165    uint32_t gicdPidr1;
166    uint32_t gicdPidr2;
167    uint32_t gicdPidr3;
168    uint32_t gicdPidr4;
169
170  public:
171
172    static const uint32_t ADDR_RANGE_SIZE = 0x10000;
173    static const uint32_t IDBITS = 0xf;
174
175  protected:
176
177    void activateIRQ(uint32_t int_id);
178    void deactivateIRQ(uint32_t int_id);
179    void fullUpdate();
180    Gicv3::GroupId getIntGroup(int int_id) const;
181
182    inline bool
183    groupEnabled(Gicv3::GroupId group) const
184    {
185        if (DS == 0) {
186            switch (group) {
187              case Gicv3::G0S:
188                return EnableGrp0;
189
190              case Gicv3::G1S:
191                return EnableGrp1S;
192
193              case Gicv3::G1NS:
194                return EnableGrp1NS;
195
196              default:
197                panic("Gicv3Distributor::groupEnabled(): "
198                        "invalid group!\n");
199            }
200        } else {
201            switch (group) {
202              case Gicv3::G0S:
203                return EnableGrp0;
204
205              case Gicv3::G1S:
206              case Gicv3::G1NS:
207                return EnableGrp1NS;
208
209              default:
210                panic("Gicv3Distributor::groupEnabled(): "
211                        "invalid group!\n");
212            }
213        }
214    }
215
216    Gicv3::IntStatus intStatus(uint32_t int_id) const;
217
218    inline bool isNotSPI(uint32_t int_id) const
219    {
220        if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) {
221            return true;
222        } else {
223            return false;
224        }
225    }
226
227    inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
228    {
229        return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
230    }
231
232    void serialize(CheckpointOut & cp) const override;
233    void unserialize(CheckpointIn & cp) override;
234    void update();
235    Gicv3CPUInterface* route(uint32_t int_id);
236
237  public:
238
239    Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
240
241    void deassertSPI(uint32_t int_id);
242    void clearIrqCpuInterface(uint32_t int_id);
243    void init();
244    uint64_t read(Addr addr, size_t size, bool is_secure_access);
245    void sendInt(uint32_t int_id);
246    void write(Addr addr, uint64_t data, size_t size,
247               bool is_secure_access);
248};
249
250#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
251