| /gem5/src/arch/riscv/ |
| H A D | tlb.hh | 97 void flushAll() override; member in class:RiscvISA::TLB
109 void serialize(CheckpointOut &cp) const override; member in class:RiscvISA::TLB
110 void unserialize(CheckpointIn &cp) override; member in class:RiscvISA::TLB
112 void regStats() override; member in class:RiscvISA::TLB
115 const RequestPtr &req, ThreadContext *tc, Mode mode) override; member in class:RiscvISA::TLB
118 Translation *translation, Mode mode) override; member in class:RiscvISA::TLB
121 ThreadContext *tc, Mode mode) const override; member in class:RiscvISA::TLB
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| /gem5/src/mem/ |
| H A D | physical.hh | 244 void serialize(CheckpointOut &cp) const override; member in class:PhysicalMemory
261 void unserialize(CheckpointIn &cp) override; member in class:PhysicalMemory
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| H A D | bridge.hh | 321 PortID idx=InvalidPortID) override; member in class:Bridge
323 void init() override; member in class:Bridge
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| H A D | packet_queue.hh | 222 DrainState drain() override; member in class:PacketQueue
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| H A D | simple_mem.hh | 94 Tick recvAtomic(PacketPtr pkt) override; member in class:SimpleMemory::MemoryPort
96 PacketPtr pkt, MemBackdoorPtr &_backdoor) override; member in class:SimpleMemory::MemoryPort
97 void recvFunctional(PacketPtr pkt) override; member in class:SimpleMemory::MemoryPort
98 bool recvTimingReq(PacketPtr pkt) override; member in class:SimpleMemory::MemoryPort
99 void recvRespRetry() override; member in class:SimpleMemory::MemoryPort
100 AddrRangeList getAddrRanges() const override; member in class:SimpleMemory::MemoryPort
181 DrainState drain() override; member in class:SimpleMemory
184 PortID idx=InvalidPortID) override; member in class:SimpleMemory
185 void init() override; member in class:SimpleMemory
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| H A D | page_table.hh | 161 void serialize(CheckpointOut &cp) const override; member in class:EmulationPageTable
162 void unserialize(CheckpointIn &cp) override; member in class:EmulationPageTable
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| H A D | port.hh | 95 void bind(Port &peer) override; member in class:MasterPort
100 void unbind() override; member in class:MasterPort
411 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override; member in class:SlavePort
[all...] |
| /gem5/src/sim/power/ |
| H A D | thermal_model.hh | 67 void serialize(CheckpointOut &cp) const override; member in class:ThermalResistor
68 void unserialize(CheckpointIn &cp) override; member in class:ThermalResistor
76 double step) const override; member in class:ThermalResistor
96 void serialize(CheckpointOut &cp) const override; member in class:ThermalCapacitor
97 void unserialize(CheckpointIn &cp) override; member in class:ThermalCapacitor
100 double step) const override; member in class:ThermalCapacitor
129 double step) const override; member in class:ThermalReference
131 void serialize(CheckpointOut &cp) const override; member in class:ThermalReference
132 void unserialize(CheckpointIn &cp) override; member in class:ThermalReference
164 void startup() override; member in class:ThermalModel
167 void serialize(CheckpointOut &cp) const override; member in class:ThermalModel
168 void unserialize(CheckpointIn &cp) override; member in class:ThermalModel
[all...] |
| /gem5/src/arch/alpha/ |
| H A D | isa.hh | 95 void serialize(CheckpointOut &cp) const override; member in class:AlphaISA::ISA
96 void unserialize(CheckpointIn &cp) override; member in class:AlphaISA::ISA
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| /gem5/src/dev/net/ |
| H A D | ethertap.hh | 71 void serialize(CheckpointOut &cp) const override; member in class:EtherTapBase
72 void unserialize(CheckpointIn &cp) override; member in class:EtherTapBase
104 PortID idx=InvalidPortID) override; member in class:EtherTapBase
151 void serialize(CheckpointOut &cp) const override; member in class:EtherTapStub
152 void unserialize(CheckpointIn &cp) override; member in class:EtherTapStub
167 void recvReal(int revent) override; member in class:EtherTapStub
168 bool sendReal(const void *data, size_t len) override; member in class:EtherTapStub
190 void recvReal(int revent) override; member in class:EtherTap
191 bool sendReal(const void *data, size_t len) override; member in class:EtherTap
[all...] |
| /gem5/src/mem/cache/prefetch/ |
| H A D | sbooe.hh | 149 void notifyFill(const PacketPtr& pkt) override; member in class:SBOOEPrefetcher
155 std::vector<AddrPriority> &addresses) override; member in class:SBOOEPrefetcher
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| H A D | stride.hh | 176 std::vector<AddrPriority> &addresses) override; member in class:StridePrefetcher
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| H A D | irregular_stream_buffer.hh | 129 std::vector<AddrPriority> &addresses) override; member in class:IrregularStreamBufferPrefetcher
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| H A D | pif.hh | 167 void notify(const Addr& pc) override; member in class:PIFPrefetcher::PrefetchListenerPC
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| H A D | spatio_temporal_memory_streaming.hh | 194 std::vector<AddrPriority> &addresses) override; member in class:STeMSPrefetcher
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| /gem5/src/mem/qos/ |
| H A D | mem_sink.hh | 131 DrainState drain() override; member in class:QoS::MemSinkCtrl
140 Port &getPort(const std::string &if_name, PortID=InvalidPortID) override; member in class:QoS::MemSinkCtrl
145 void init() override; member in class:QoS::MemSinkCtrl
242 void regStats() override; member in class:QoS::MemSinkCtrl
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| /gem5/src/arch/x86/ |
| H A D | process.hh | 83 SyscallDesc* getDesc(int callnum) override; member in class:X86ISA::X86Process
86 SyscallReturn return_value) override; member in class:X86ISA::X86Process
88 Process *process, RegVal flags) override; member in class:X86ISA::X86Process
136 void initState() override; member in class:X86ISA::X86_64Process
138 RegVal getSyscallArg(ThreadContext *tc, int &i) override; member in class:X86ISA::X86_64Process
141 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; member in class:X86ISA::X86_64Process
143 Process *process, RegVal flags) override; member in class:X86ISA::X86_64Process
178 void initState() override; member in class:X86ISA::I386Process
181 Fault *fault) override; member in class:X86ISA::I386Process
182 RegVal getSyscallArg(ThreadContext *tc, int &i) override; member in class:X86ISA::I386Process
183 RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; member in class:X86ISA::I386Process
184 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; member in class:X86ISA::I386Process
186 Process *process, RegVal flags) override; member in class:X86ISA::I386Process
[all...] |
| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_record.hh | 101 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecord::TraceInstEntry
136 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecord::TraceRegEntry
172 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecord::TraceMemEntry
185 virtual void dump() override; member in class:Trace::TarmacTracerRecord
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| /gem5/src/cpu/pred/ |
| H A D | tage_sc_l.hh | 77 virtual TAGEBase::BranchInfo *makeBranchInfo() override; member in class:TAGE_SC_L_TAGE
90 void calculateParameters() override; member in class:TAGE_SC_L_TAGE
92 void buildTageTables() override; member in class:TAGE_SC_L_TAGE
95 ThreadID tid, Addr branch_pc, TAGEBase::BranchInfo* bi) override; member in class:TAGE_SC_L_TAGE
97 unsigned getUseAltIdx(TAGEBase::BranchInfo* bi, Addr branch_pc) override; member in class:TAGE_SC_L_TAGE
102 Addr target) override; member in class:TAGE_SC_L_TAGE
104 int bindex(Addr pc_in) const override; member in class:TAGE_SC_L_TAGE
105 int gindex(ThreadID tid, Addr pc, int bank) const override; member in class:TAGE_SC_L_TAGE
107 int F(int phist, int size, int bank) const override; member in class:TAGE_SC_L_TAGE
109 virtual uint16_t gtag(ThreadID tid, Addr pc, int bank) const override member in class:TAGE_SC_L_TAGE
112 Addr target) override; member in class:TAGE_SC_L_TAGE
118 void adjustAlloc(bool & alloc, bool taken, bool pred_taken) override; member in class:TAGE_SC_L_TAGE
121 TAGEBase::BranchInfo* bi, int nrand) override = 0; member in class:TAGE_SC_L_TAGE
123 void handleUReset() override; member in class:TAGE_SC_L_TAGE
126 Addr branch_pc, bool taken, TAGEBase::BranchInfo* bi) override = 0; member in class:TAGE_SC_L_TAGE
131 TAGEBase::BranchInfo* tage_bi) const override; member in class:TAGE_SC_L_TAGE
133 void extraAltCalc(TAGEBase::BranchInfo* bi) override; member in class:TAGE_SC_L_TAGE
144 virtual bool calcConf(int index) const override; member in class:TAGE_SC_L_LoopPredictor
145 virtual bool optionalAgeInc() const override; member in class:TAGE_SC_L_LoopPredictor
155 ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) override; member in class:TAGE_SC_L
157 void regStats() override; member in class:TAGE_SC_L
161 Addr corrTarget = MaxAddr) override; member in class:TAGE_SC_L
[all...] |
| /gem5/src/learning_gem5/part2/ |
| H A D | simple_cache.hh | 96 AddrRangeList getAddrRanges() const override; member in class:SimpleCache::CPUSidePort
118 void recvFunctional(PacketPtr pkt) override; member in class:SimpleCache::CPUSidePort
128 bool recvTimingReq(PacketPtr pkt) override; member in class:SimpleCache::CPUSidePort
135 void recvRespRetry() override; member in class:SimpleCache::CPUSidePort
172 bool recvTimingResp(PacketPtr pkt) override; member in class:SimpleCache::MemSidePort
179 void recvReqRetry() override; member in class:SimpleCache::MemSidePort
188 void recvRangeChange() override; member in class:SimpleCache::MemSidePort
319 PortID idx=InvalidPortID) override; member in class:SimpleCache
324 void regStats() override; member in class:SimpleCache
[all...] |
| /gem5/src/dev/ |
| H A D | intpin.hh | 72 void bind(Port &peer) override; member in class:IntSinkPinBase
73 void unbind() override; member in class:IntSinkPinBase
106 void bind(Port &peer) override; member in class:IntSourcePinBase
107 void unbind() override; member in class:IntSourcePinBase
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | gem5_to_tlm.hh | 195 ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override; member in class:sc_gem5::Gem5ToTlmBridge
206 void before_end_of_elaboration() override; member in class:sc_gem5::Gem5ToTlmBridge
[all...] |
| H A D | tlm_to_gem5.hh | 164 ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override; member in class:sc_gem5::TlmToGem5Bridge
175 void before_end_of_elaboration() override; member in class:sc_gem5::TlmToGem5Bridge
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| /gem5/src/dev/x86/ |
| H A D | i8259.hh | 48 void init() override; member in class:X86ISA::I8259
106 Tick read(PacketPtr pkt) override; member in class:X86ISA::I8259
107 Tick write(PacketPtr pkt) override; member in class:X86ISA::I8259
126 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::I8259
127 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::I8259
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| H A D | i8254.hh | 96 Tick read(PacketPtr pkt) override; member in class:X86ISA::I8254
98 Tick write(PacketPtr pkt) override; member in class:X86ISA::I8254
124 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::I8254
125 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::I8254
127 void startup() override; member in class:X86ISA::I8254
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