Searched full:pstate (Results 1 - 25 of 34) sorted by relevance

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/gem5/src/arch/sparc/
H A Dinterrupts.hh140 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
148 if (pstate.ie) {
171 if (pstate.ie) {
185 } // !hpriv && pstate.ie
197 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
205 if (pstate.ie) {
228 if (pstate.ie) {
243 } // !hpriv && pstate
[all...]
H A Dfaults.cc290 // PSTATE.priv is set to 1 here. The manual says it should be 0, but
292 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
293 pstate.priv = 1;
294 tc->setMiscReg(MISCREG_PSTATE, pstate);
307 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
318 Addr pcMask = pstate.am ? mask(32) : mask(64);
326 // set TSTATE.pstate to pstate
386 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
512 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
571 PSTATE pstate = 0; local
[all...]
H A Dutility.hh60 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); local
62 return !(pstate.priv || hpstate.hpriv);
H A Disa.cc46 static PSTATE
49 PSTATE mask = 0;
61 static const PSTATE PstateMask = buildPstateMask();
135 pstate = 0;
200 (uint64_t)pstate.priv << 2 |
201 (uint64_t)pstate.am << 3 |
251 return (RegVal)pstate;
444 pstate = (val & PstateMask);
590 pstate = val & PstateMask;
658 SERIALIZE_SCALAR(pstate);
735 uint16_t pstate; local
[all...]
H A Dremote_gdb.cc183 PSTATE pstate = context->readMiscReg(MISCREG_PSTATE); local
184 r.psr = htobe((uint32_t)pstate);
201 PSTATE pstate = context->readMiscReg(MISCREG_PSTATE); local
204 pstate << 8 |
245 PSTATE pstate = context()->readMiscReg(MISCREG_PSTATE); local
246 if (pstate.am) {
H A Dprocess.cc167 PSTATE pstate = 0; local
168 pstate.ie = 1;
169 pstate.am = 1;
170 tc->setMiscReg(MISCREG_PSTATE, pstate);
182 PSTATE pstate = 0; local
183 pstate.ie = 1;
184 tc->setMiscReg(MISCREG_PSTATE, pstate);
539 PSTATE pstat local
[all...]
H A Dmiscregs.hh127 BitUnion16(PSTATE)
137 EndBitUnion(PSTATE)
H A Disa.hh77 PSTATE pstate; // Process State Register member in class:SparcISA::ISA
181 bool isPriv() { return hpstate.hpriv || pstate.priv; }
H A Dua2005.cc78 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc162 inform(" %s: %s\n", "PSTATE", getAndFormatOneReg(INT_REG(regs.pstate)));
220 // update pstate register state
230 DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
231 setOneReg(INT_REG(regs.pstate), static_cast<uint64_t>(cpsr));
286 // Update pstate thread context
287 const CPSR cpsr(getOneRegU64(INT_REG(regs.pstate)));
288 DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
/gem5/util/cpt_upgraders/
H A Disa-is-simobject.py10 "tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate",
/gem5/src/arch/sparc/isa/formats/mem/
H A Dutil.isa185 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
189 if ((!Pstate.priv && !Hpstate.hpriv &&
193 else if (asiIsAsIfUser((ASI)EXT_ASI) && !Pstate.priv)
199 EA = Pstate.am ? EA<31:0> : EA;
H A Dblockmem.isa184 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
/gem5/src/arch/sparc/isa/
H A Dbase.isa133 PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE);
134 if (pstate.pef && xc->readMiscReg(MISCREG_FPRS) & 0x4) {
H A Doperands.isa45 'pstate' : 'PSTATE',
173 'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59),
H A Ddecoder.isa142 R15 = midVal = (Pstate.am ? (PC)<31:0> : PC);
330 if (Pstate.am)
359 if (Pstate.am && !Hpstate.hpriv)
386 0x06: Priv::rdprpstate({{Rd = Pstate;}});
482 if (Fprs<2:> == 0 || Pstate.pef == 0)
537 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
539 if (Pstate.priv && !Hpstate.hpriv)
553 if (Pstate.priv && !Hpstate.hpriv)
1000 if (Pstate.am)
1076 Pstate
[all...]
/gem5/src/arch/arm/insts/
H A Dmisc64.hh160 * as if it was a MSR PSTATE REG instruction.
162 * which PSTATE field is being set/cleared.
H A Dpseudo.hh125 * (PSTATE.IL = 1 or CPSR.IL = 1).
H A Dmisc64.cc333 panic("Not a valid PSTATE field register\n");
/gem5/util/statetrace/arch/sparc/
H A Dtracechild.hh66 FSR, FPRS, PC, NPC, Y, CWP, PSTATE, ASI, CCR, enumerator in enum:SparcTraceChild::RegNum
/gem5/src/arch/sparc/isa/formats/
H A Dpriv.isa118 check_code = "(%s) && !(Pstate.priv || Hpstate.hpriv)" % extraCond
/gem5/src/arch/mips/
H A Dpra_constants.hh321 Bitfield<7, 6> pState; member in namespace:MipsISA
/gem5/src/arch/riscv/
H A Dpra_constants.hh321 Bitfield<7, 6> pState; member in namespace:RiscvISA
/gem5/src/arch/arm/
H A Dinterrupts.hh128 INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
/gem5/src/arch/sparc/insts/
H A Dstatic_inst.cc206 ccprintf(os, "%%pstate");

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