Searched refs:tCCD_L (Results 1 - 3 of 3) sorted by relevance
/gem5/src/mem/ |
H A D | DRAMCtrl.py | 190 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") variable in class:DRAMCtrl 196 tCCD_L_WR = Param.Latency(Self.tCCD_L, 582 # @2400 data rate, tCCD_L is 6 CK 586 tCCD_L = '5ns'; variable in class:DDR4_2400_16x4 1025 # @1000MHz data rate, tCCD_L is 3 CK 1029 tCCD_L = '3ns'; variable in class:GDDR5_4000_2x32
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H A D | dram_ctrl.cc | 88 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 165 // tCCD_L should be greater than minimal, back-to-back burst delay 166 if (tCCD_L <= tBURST) { 167 fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 169 tCCD_L, tBURST, bankGroupsPerRank); 1157 // bank (add a max with tCCD/tCCD_L/tCCD_L_WR here) 1163 // before tCCD_L. Different bank group timing requirement is 1170 // tCCD_L is default requirement for same BG timing 1174 tCCD_L [all...] |
H A D | dram_ctrl.hh | 992 const Tick tCCD_L; member in class:DRAMCtrl
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