/gem5/src/cpu/ |
H A D | nativetrace.cc | 48 int port = 8000; local 49 while (!native_listener.listen(port, true)) 51 DPRINTF(GDBMisc, "Can't bind port %d\n", port); 52 port++; 54 ccprintf(cerr, "Listening for native process on port %d\n", port);
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/gem5/util/tlm/src/ |
H A D | master_transactor.cc | 50 SC_REPORT_ERROR(name, "No port name specified!\n"); 57 auto* port = sim_control->getMasterPort(portName); local 59 port->bindToTransactor(this);
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H A D | slave_transactor.cc | 50 SC_REPORT_ERROR(name, "No port name specified!\n"); 57 auto* port = sim_control->getSlavePort(portName); local 59 port->bindToTransactor(this);
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H A D | sc_peq.hh | 55 OWNER& port; member in class:Gem5SystemC::PayloadEvent 65 void process() { (port.*handler)(this, *t, p); } 75 : port(port_) 96 port.owner.wakeupEventQueue(nextEventTick); 97 port.owner.schedule(this, nextEventTick);
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/gem5/src/systemc/core/ |
H A D | port.hh | 63 void finalizePort(StaticSensitivityPort *port); 92 interface(interface), port(nullptr) 95 explicit Binding(::sc_core::sc_port_base *port) : argument 96 interface(nullptr), port(port) 100 ::sc_core::sc_port_base *port; member in struct:sc_gem5::Port::Binding 105 Sensitivity(StaticSensitivityPort *port) : argument 106 port(port), finder(nullptr) 110 port(nullpt 113 StaticSensitivityPort *port; member in struct:sc_gem5::Port::Sensitivity 149 bind(::sc_core::sc_port_base *port) argument [all...] |
H A D | sc_sensitive.cc | 114 sc_sensitive::operator () (::sc_gem5::Process *p, const sc_in<bool> &port) argument 117 sc_gem5::newStaticSensitivityFinder(p, &port.pos()); 122 const sc_in<sc_dt::sc_logic> &port) 125 sc_gem5::newStaticSensitivityFinder(p, &port.pos()); 129 sc_sensitive::operator () (::sc_gem5::Process *p, const sc_inout<bool> &port) argument 132 sc_gem5::newStaticSensitivityFinder(p, &port.pos()); 137 const sc_inout<sc_dt::sc_logic> &port) 140 sc_gem5::newStaticSensitivityFinder(p, &port.pos()); 121 operator ()(::sc_gem5::Process *p, const sc_in<sc_dt::sc_logic> &port) argument 136 operator ()(::sc_gem5::Process *p, const sc_inout<sc_dt::sc_logic> &port) argument
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H A D | port.cc | 30 #include "systemc/core/port.hh" 42 Port::finalizePort(StaticSensitivityPort *port) argument 45 port->addEvent(&getInterface(i)->default_event()); 69 Port::sensitive(StaticSensitivityPort *port) argument 72 finalizePort(port); 74 sensitivities.push_back(new Sensitivity(port)); 106 b->port->_gem5Port->finalize(); 107 addInterfaces(b->port); 115 if (s->port) 116 finalizePort(s->port); [all...] |
H A D | sc_spawn.cc | 179 sc_spawn_options::reset_signal_is(const sc_in<bool> &port, bool value) argument 181 _in_resets.emplace_back(&port, value, true); 185 sc_spawn_options::reset_signal_is(const sc_inout<bool> &port, bool value) argument 187 _inout_resets.emplace_back(&port, value, true); 191 sc_spawn_options::reset_signal_is(const sc_out<bool> &port, bool value) argument 193 _out_resets.emplace_back(&port, value, true); 205 sc_spawn_options::async_reset_signal_is(const sc_in<bool> &port, bool value) argument 207 _in_resets.emplace_back(&port, value, false); 211 sc_spawn_options::async_reset_signal_is(const sc_inout<bool> &port, bool value) argument 213 _inout_resets.emplace_back(&port, valu 217 async_reset_signal_is(const sc_out<bool> &port, bool value) argument [all...] |
/gem5/src/sim/ |
H A D | debug.hh | 71 // Remote gdb base port. 0 disables remote gdb. 72 void setRemoteGDBPort(int port);
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/gem5/src/cpu/simple/ |
H A D | noncaching.hh | 58 Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override;
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H A D | noncaching.cc | 57 NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) argument 63 return port.sendAtomic(pkt);
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/gem5/src/mem/ |
H A D | SimpleMemory.py | 48 port = SlavePort("Slave ports") variable in class:SimpleMemory
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H A D | DRAMSim2.py | 46 # A single port for now 47 port = SlavePort("Slave port") variable in class:DRAMSim2
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H A D | ExternalMaster.py | 48 port = MasterPort("Master port") variable in class:ExternalMaster 50 port_type = Param.String('stub', 'Registered external port handler' 51 ' to pass this port to in instantiation') 52 port_data = Param.String('stub', 'A string to pass to the port' 54 ' the port should be bound/bindable/discoverable') 56 system = Param.System(Parent.any, 'System this external port belongs to')
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H A D | ExternalSlave.py | 45 port = SlavePort("Slave port") variable in class:ExternalSlave 48 ' this port\'s external agent') 50 port_type = Param.String('stub', 'Registered external port handler' 51 ' to pass this port to in instantiation') 52 port_data = Param.String('stub', 'A string to pass to the port' 54 ' the port should be bound/bindable/discoverable')
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/gem5/src/systemc/tests/systemc/tmp/others/sc_writer_bug/ |
H A D | sc_writer_bug.cpp | 15 sc_inout<bool> port;
member in struct:M 20 : port("port")
29 port.write(true);
30 cout << "port written in " << name() << " at " << sc_time_stamp()
51 m1->port.bind(multi_sig_1);
52 m2->port.bind(multi_sig_1);
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/gem5/src/systemc/tlm_bridge/ |
H A D | sc_peq.hh | 55 OWNER& port; member in class:Gem5SystemC::PayloadEvent 65 void process() { (port.*handler)(this, *t, p); } 75 : port(port_) 96 port.owner.wakeupEventQueue(nextEventTick); 97 port.owner.schedule(this, nextEventTick);
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/gem5/src/base/ |
H A D | socket.hh | 57 virtual bool listen(int port, bool reuse = true);
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_spawn_options.cpp | 92 async_reset_signal_is ( const Port & port, bool level ) \ 95 new sc_spawn_reset< Port >(true, port, level) ); \ 100 reset_signal_is ( const Port & port, bool level ) \ 103 new sc_spawn_reset< Port >(false, port, level) ); \
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/gem5/src/cpu/testers/directedtest/ |
H A D | InvalidateGenerator.cc | 57 MasterPort* port; local 71 port = m_directed_tester->getCpuPort(m_active_read_node); 76 port = m_directed_tester->getCpuPort(m_active_inv_node); 83 if (port->sendTimingReq(pkt)) {
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/gem5/src/base/vnc/ |
H A D | Vnc.py | 54 port = Param.TcpPort(5900, "listen port") variable in class:VncServer
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/gem5/src/mem/qos/ |
H A D | QoSMemSinkCtrl.py | 45 port = SlavePort("Slave ports") variable in class:QoSMemSinkCtrl
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/gem5/src/dev/serial/ |
H A D | Terminal.py | 52 port = Param.TcpPort(3456, "listen port") variable in class:Terminal
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/gem5/src/mem/ruby/system/ |
H A D | RubyPort.hh | 133 { panic("recvFunctional should never be called on pio slave port!"); } 140 MemSlavePort *port; member in struct:RubyPort::SenderState 141 SenderState(MemSlavePort * _port) : port(_port) 176 * Called by the PIO port when receiving a timing response. 179 * @param master_port_id Port id of the PIO port 195 bool onRetryList(MemSlavePort * port) argument 197 return (std::find(retryList.begin(), retryList.end(), port) != 200 void addToRetryList(MemSlavePort * port) argument 202 if (onRetryList(port)) return; 203 retryList.push_back(port); [all...] |
/gem5/configs/example/ |
H A D | hmctest.py | 25 external port for SystemC TLM co-simulation. Default:\ 68 system.tgen[i].port = system.membus.slave 69 # connect the system port even if it is not used in this example 73 system.tgen[i].port = system.membus.slave 76 system.tgen[2].port = hh.lmonitor[2].slave 78 system.tgen[3].port = hh.lmonitor[3].slave 81 system.tgen[2].port = hh.seriallink[2].slave 82 system.tgen[3].port = hh.seriallink[3].slave 83 # connect the system port even if it is not used in this example 89 system.tgen[i].port [all...] |