/gem5/src/cpu/testers/traffic_gen/ |
H A D | dram_rot_gen.cc | 107 // Simply increment addr by blocksize to 109 addr += blocksize; 115 unsigned int new_col = ((addr / blocksize / 117 (pageSize / blocksize)) + 1; 125 isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts); 128 PacketPtr pkt = getPacket(addr, blocksize, 132 dataManipulated += blocksize;
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H A D | linear_gen.cc | 70 isRead ? 'r' : 'w', nextAddr, blocksize); 73 dataManipulated += blocksize; 75 PacketPtr pkt = getPacket(nextAddr, blocksize, 79 nextAddr += blocksize;
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H A D | random_gen.cc | 72 addr -= addr % blocksize; 75 isRead ? 'r' : 'w', addr, blocksize); 78 dataManipulated += blocksize; 81 return getPacket(addr, blocksize,
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H A D | dram_gen.cc | 120 // Simply increment addr by blocksize to increment 122 addr += blocksize; 127 unsigned int new_col = ((addr / blocksize / 129 (pageSize / blocksize)) + 1; 137 isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts); 140 PacketPtr pkt = getPacket(addr, blocksize, 144 dataManipulated += blocksize; 160 addr -= addr % blocksize; 173 unsigned int columns_per_page = pageSize / blocksize;
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H A D | trace_gen.cc | 85 element.blocksize = pkt_msg.size(); 148 currElement.blocksize, 153 currElement.blocksize, 160 nextElement.blocksize,
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H A D | base_gen.cc | 91 blocksize(_blocksize), cacheLineSize(cacheline_size), 95 if (blocksize > cacheLineSize) 98 blocksize, cacheLineSize);
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H A D | traffic_gen.cc | 193 Addr blocksize; local 199 blocksize >> min_period >> max_period >> data_limit; 203 mode, start_addr, end_addr, blocksize, min_period, 209 end_addr, blocksize, 215 end_addr, blocksize, 236 blocksize, page_size); 242 if (stride_size > blocksize) { 243 num_seq_pkts = divCeil(stride_size, blocksize); 246 stride_size, blocksize, num_seq_pkts); 251 end_addr, blocksize, [all...] |
H A D | trace_gen.hh | 80 Addr blocksize; member in struct:TraceGen::TraceElement
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H A D | base.hh | 264 Addr start_addr, Addr end_addr, Addr blocksize, 270 Addr start_addr, Addr end_addr, Addr blocksize, 276 Addr start_addr, Addr end_addr, Addr blocksize, 286 Addr start_addr, Addr end_addr, Addr blocksize,
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H A D | base.cc | 373 Addr start_addr, Addr end_addr, Addr blocksize, 379 end_addr, blocksize, 387 Addr start_addr, Addr end_addr, Addr blocksize, 393 end_addr, blocksize, 401 Addr start_addr, Addr end_addr, Addr blocksize, 412 end_addr, blocksize, 425 Addr start_addr, Addr end_addr, Addr blocksize, 438 end_addr, blocksize, 372 createLinear(Tick duration, Addr start_addr, Addr end_addr, Addr blocksize, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument 386 createRandom(Tick duration, Addr start_addr, Addr end_addr, Addr blocksize, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument 400 createDram(Tick duration, Addr start_addr, Addr end_addr, Addr blocksize, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, unsigned int addr_mapping, unsigned int nbr_of_ranks) argument 424 createDramRot(Tick duration, Addr start_addr, Addr end_addr, Addr blocksize, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, unsigned int addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank) argument
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H A D | base_gen.hh | 155 const Addr blocksize; member in class:StochasticGen
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/gem5/ext/mcpat/ |
H A D | arch_const.h | 38 unsigned int blocksize; member in struct:__anon52
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.hh | 360 Addr blocksize; member in struct:TraceCPU::FixedRetryGen::TraceElement
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H A D | trace_cpu.cc | 1085 if (!send(currElement.addr, currElement.blocksize, 1142 currElement.blocksize, 1501 element->blocksize = pkt_msg.size();
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