Searched refs:VecPredRegClass (Results 1 - 10 of 10) sorted by relevance
/gem5/src/cpu/o3/ |
H A D | free_list.hh | 284 case VecPredRegClass: 317 case VecPredRegClass:
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H A D | rename_map.hh | 242 case VecPredRegClass: 285 case VecPredRegClass: 331 case VecPredRegClass:
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H A D | regfile.cc | 118 vecPredRegIds.emplace_back(VecPredRegClass, phys_reg, flat_reg_idx++); 211 case VecPredRegClass:
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H A D | cpu.cc | 285 renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg); 287 RegId(VecPredRegClass, ridx), phys_reg); 1372 RegId(VecPredRegClass, reg_idx)); 1382 RegId(VecPredRegClass, reg_idx)); 1445 RegId(VecPredRegClass, reg_idx));
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H A D | dyn_inst.hh | 234 case VecPredRegClass:
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H A D | rename_impl.hh | 1090 case VecPredRegClass:
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/gem5/src/cpu/ |
H A D | reg_class.hh | 63 VecPredRegClass, enumerator in enum:RegClass 161 bool isVecPredReg() const { return regClass == VecPredRegClass; } 191 case VecPredRegClass:
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H A D | thread_context.cc | 93 RegId rid(VecPredRegClass, i);
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/gem5/src/cpu/minor/ |
H A D | scoreboard.cc | 80 case VecPredRegClass:
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/gem5/src/arch/arm/ |
H A D | isa.hh | 461 case VecPredRegClass: 462 return RegId(VecPredRegClass,
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