/gem5/src/mem/ruby/common/ |
H A D | Address.hh | 41 Addr bitSelect(Addr addr, unsigned int small, unsigned int big); 42 Addr bitRemove(Addr addr, unsigned int small, unsigned int big); 43 Addr maskLowOrderBits(Addr addr, unsigned int number); 44 Addr maskHighOrderBits(Addr addr, unsigned int number); 45 Addr shiftLowOrderBits(Addr add [all...] |
H A D | Address.cc | 33 Addr 34 bitSelect(Addr addr, unsigned int small, unsigned int big) 41 Addr mask = ~((Addr)~0 << (big + 1)); 43 Addr partial = (addr & mask); 48 Addr 49 bitRemove(Addr addr, unsigned int small, unsigned int big) 56 Addr mask = (Addr)~0 >> small; 59 Addr mas [all...] |
/gem5/src/arch/mips/ |
H A D | vtophys.hh | 43 Addr vtophys(Addr vaddr); 44 Addr vtophys(ThreadContext *tc, Addr vaddr);
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H A D | vtophys.cc | 46 Addr 47 MipsISA::vtophys(Addr vaddr) 53 Addr 54 MipsISA::vtophys(ThreadContext *tc, Addr addr)
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H A D | isa_traits.hh | 50 const Addr PageShift = 13; 51 const Addr PageBytes = ULL(1) << PageShift; 52 const Addr Page_Mask = ~(PageBytes - 1); 53 const Addr PageOffset = PageBytes - 1; 61 const Addr PteShift = 3; 62 const Addr NPtePageShift = PageShift - PteShift; 63 const Addr NPtePage = ULL(1) << NPtePageShift; 64 const Addr PteMask = NPtePage - 1; 70 const Addr USegBase = ULL(0x0); 71 const Addr USegEn [all...] |
/gem5/src/arch/sparc/ |
H A D | vtophys.hh | 42 Addr vtophys(Addr vaddr); 43 Addr vtophys(ThreadContext *tc, Addr vaddr);
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/gem5/src/arch/x86/ |
H A D | vtophys.hh | 50 Addr vtophys(Addr vaddr); 51 Addr vtophys(ThreadContext *tc, Addr vaddr);
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H A D | isa_traits.hh | 56 const Addr PageShift = 12; 57 const Addr PageBytes = ULL(1) << PageShift;
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/gem5/src/arch/arm/ |
H A D | vtophys.hh | 43 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 45 Addr vtophys(Addr vaddr); 46 Addr vtophys(ThreadContext *tc, Addr vaddr); 47 bool virtvalid(ThreadContext *tc, Addr vaddr);
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H A D | isa_traits.hh | 60 const Addr PageShift = 12; 61 const Addr PageBytes = ULL(1) << PageShift; 62 const Addr Page_Mask = ~(PageBytes - 1); 63 const Addr PageOffset = PageBytes - 1; 71 const Addr PteShift = 3; 72 const Addr NPtePageShift = PageShift - PteShift; 73 const Addr NPtePage = ULL(1) << NPtePageShift; 74 const Addr PteMask = NPtePage - 1; 80 const Addr USegBase = ULL(0x0); 81 const Addr USegEn [all...] |
/gem5/src/mem/cache/tags/indexing_policies/ |
H A D | skewed_associative.hh | 99 Addr hash(const Addr addr) const; 108 Addr dehash(const Addr addr) const; 118 Addr skew(const Addr addr, const uint32_t way) const; 129 Addr deskew(const Addr addr, const uint32_t way) const; 138 uint32_t extractSet(const Addr addr, const uint32_t way) const; 162 std::vector<ReplaceableEntry*> getPossibleEntries(const Addr add [all...] |
/gem5/src/arch/power/ |
H A D | vtophys.cc | 35 Addr 36 PowerISA::vtophys(Addr vaddr) 41 Addr 42 PowerISA::vtophys(ThreadContext *tc, Addr addr)
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H A D | isa_traits.hh | 51 const Addr PageShift = 12; 52 const Addr PageBytes = ULL(1) << PageShift; 53 const Addr Page_Mask = ~(PageBytes - 1); 54 const Addr PageOffset = PageBytes - 1; 56 const Addr PteShift = 3; 57 const Addr NPtePageShift = PageShift - PteShift; 58 const Addr NPtePage = ULL(1) << NPtePageShift; 59 const Addr PteMask = NPtePage - 1;
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H A D | vtophys.hh | 46 Addr vtophys(Addr vaddr); 47 Addr vtophys(ThreadContext *tc, Addr vaddr); 49 inline Addr 50 PteAddr(Addr a)
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H A D | pagetable.hh | 50 static const Addr ImplMask = (ULL(1) << ImplBits) - 1; 51 static const Addr UnImplMask = ~ImplMask; 53 Addr addr; 55 VAddr(Addr a) 59 operator Addr() const 65 &operator=(Addr a) 71 Addr 77 Addr 83 Addr 89 Addr [all...] |
/gem5/src/arch/riscv/ |
H A D | vtophys.hh | 48 inline Addr 49 vtophys(Addr vaddr) 55 inline Addr 56 vtophys(ThreadContext *tc, Addr vaddr)
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H A D | isa_traits.hh | 60 const Addr PageShift = 12; 61 const Addr PageBytes = ULL(1) << PageShift;
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/gem5/src/arch/null/ |
H A D | isa_traits.hh | 47 const Addr PageShift = 12; 48 const Addr PageBytes = ULL(1) << PageShift;
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/gem5/src/dev/sparc/ |
H A D | t1000.hh | 83 virtual Addr pciToDma(Addr pciAddr) const; 88 virtual Addr calcPciConfigAddr(int bus, int dev, int func); 93 virtual Addr calcPciIOAddr(Addr addr); 98 virtual Addr calcPciMemAddr(Addr addr);
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/gem5/src/base/loader/ |
H A D | raw_object.hh | 44 virtual bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, 45 Addr offset = 0, Addr addr_mask = maxAddr); 46 virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, 47 Addr offset = 0, 48 Addr addr_mask = maxAddr); 49 virtual bool loadLocalSymbols(SymbolTable *symtab, Addr base = 0, 50 Addr offset = 0, Addr addr_mask = maxAddr);
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H A D | elf_object.hh | 59 Addr _programHeaderTable; 69 Addr ldBias; 79 Addr ldMin; 80 Addr ldMax; 83 bool loadSomeSymbols(SymbolTable *symtab, int binding, Addr mask, 84 Addr base, Addr offset); 97 bool loadSections(const PortProxy& mem_proxy, Addr addr_mask = maxAddr, 98 Addr offset = 0) override; 100 virtual bool loadAllSymbols(SymbolTable *symtab, Addr bas [all...] |
H A D | object_file.hh | 89 static const Addr maxAddr = std::numeric_limits<Addr>::max(); 92 Addr mask = maxAddr, Addr offset = 0); 94 virtual bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, 95 Addr offset = 0, Addr mask = maxAddr) = 0; 96 virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, 97 Addr offset = 0, Addr mas [all...] |
/gem5/src/arch/alpha/ |
H A D | vtophys.hh | 44 PageTableEntry kernel_pte_lookup(PortProxy &mem, Addr ptbr, 47 Addr vtophys(Addr vaddr); 48 Addr vtophys(ThreadContext *tc, Addr vaddr);
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/gem5/src/base/filters/ |
H A D | bulk_bloom_filter.hh | 53 int hash(Addr addr, int hash_number) const override; 57 Addr permute(Addr addr) const;
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/gem5/src/mem/ |
H A D | page_table.hh | 55 Addr paddr; 58 Entry(Addr paddr, uint64_t flags) : paddr(paddr), flags(flags) {} 63 typedef std::unordered_map<Addr, Entry> PTable; 67 const Addr pageSize; 68 const Addr offsetMask; 76 const std::string &__name, uint64_t _pid, Addr _pageSize) : 107 Addr pageAlign(Addr a) { return (a & ~offsetMask); } 108 Addr pageOffset(Addr [all...] |