Searched hist:8206 (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/arm/isa/insts/
H A Dmult.isa8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
H A Dneon.isa8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
/gem5/src/arch/arm/
H A Dutility.hh8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
H A Dmiscregs.hh8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
H A Disa.cc8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
/gem5/configs/example/
H A Dse.py3399:8206f6b9283e Thu Oct 26 16:04:00 EDT 2006 Lisa Hsu <hsul@eecs.umich.edu> se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

configs/example/se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

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