Searched hist:3520 (Results 1 - 7 of 7) sorted by relevance
/gem5/src/arch/alpha/ | ||
H A D | interrupts.hh | 3520:4f4a2054fd85 Fri Nov 03 02:25:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | macromem.isa | 12134:604f47f63877 Wed May 24 18:35:00 EDT 2017 Gedare Bloom <gedare@rtems.org> arch-arm: fix ldm of pc interswitching branch The LDM instruction that loads to the PC causes a branch to the instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes. The interswitch is broken prior to this commit, with LDM to the PC ignoring the switch. Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05 Reviewed-on: https://gem5-review.googlesource.com/3520 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/ | ||
H A D | SConscript | 3520:4f4a2054fd85 Fri Nov 03 02:25:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the |
/gem5/src/arch/arm/isa/ | ||
H A D | operands.isa | 12134:604f47f63877 Wed May 24 18:35:00 EDT 2017 Gedare Bloom <gedare@rtems.org> arch-arm: fix ldm of pc interswitching branch The LDM instruction that loads to the PC causes a branch to the instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes. The interswitch is broken prior to this commit, with LDM to the PC ignoring the switch. Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05 Reviewed-on: https://gem5-review.googlesource.com/3520 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/cpu/simple/ | ||
H A D | base.cc | 3520:4f4a2054fd85 Fri Nov 03 02:25:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the |
/gem5/src/cpu/ | ||
H A D | base.cc | 3520:4f4a2054fd85 Fri Nov 03 02:25:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the |
H A D | base.hh | 3520:4f4a2054fd85 Fri Nov 03 02:25:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the |
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