Searched hist:12136 (Results 1 - 7 of 7) sorted by relevance
/gem5/src/arch/riscv/ | ||
H A D | decoder.cc | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
H A D | decoder.hh | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
H A D | utility.hh | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
H A D | faults.hh | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
H A D | faults.cc | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
/gem5/src/arch/riscv/isa/formats/ | ||
H A D | fp.isa | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
/gem5/src/arch/riscv/isa/ | ||
H A D | decoder.isa | 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
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