Searched hist:10860 (Results 1 - 11 of 11) sorted by relevance

/gem5/src/arch/arm/kvm/
H A DSConscript10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A Dbase_cpu.hh10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A DBaseArmKvmCPU.py10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A DArmV8KvmCPU.py10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A Dbase_cpu.cc10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A Darmv8_cpu.hh10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A Darmv8_cpu.cc10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
/gem5/src/cpu/kvm/
H A Dvm.cc10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
H A Dvm.hh10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
/gem5/configs/common/
H A DCpuConfig.py10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
/gem5/
H A DSConstruct10860:cba0f26038b4 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.

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