Searched refs:tRP (Results 1 - 5 of 5) sorted by relevance

/gem5/src/mem/
H A DDRAMCtrl.py164 tRP = Param.Latency("Row precharge time") variable in class:DRAMCtrl
245 # tRC - assumed to be tRAS + tRP
362 tRP = '13.75ns' variable in class:DDR3_1600_8x8
460 tRP = '7.7ns' variable in class:HMC_2500_1x32
518 tRP = '13.09ns' variable in class:DDR3_2133_8x8
591 tRP = '14.16ns' variable in class:DDR4_2400_16x4
757 tRP = '15ns' variable in class:LPDDR2_S4_1066_1x32
852 tRP = '18ns' variable in class:WideIO_200_1x128
930 tRP = '18ns' variable in class:LPDDR3_1600_1x32
1036 tRP variable in class:GDDR5_4000_2x32
1114 tRP = '15ns' variable in class:HBM_1000_4H_1x128
[all...]
H A Ddrampower.cc80 timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
83 timingSpec.RP = divCeil(p->tRP, p->tCK);
H A Ddram_ctrl.cc88 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
146 if (tREFI <= tRP || tREFI <= tRFC) {
147 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
148 tREFI, tRP, tRFC);
253 r->startup(curTick() + tREFI - tRP);
260 nextBurstAt = curTick() + tRP + tRCD;
279 latency = tRP + tRCD + tCL;
1069 Tick pre_done_at = pre_at + tRP;
1301 nextReqTime = nextBurstAt - (tRP
[all...]
H A Ddram_ctrl.hh995 const Tick tRP; member in class:DRAMCtrl
1050 * and access, it is tRP + tRCD + tCL.
/gem5/configs/dram/
H A Dlow_power_sweep.py159 #The itt value when set to (tRAS + tRP + tCK) covers the case where
162 # between a write and power down entry will be tRCD + tCL + tWR + tRP + tCK.
166 system.mem_ctrls[0].tRP.value +

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