Searched refs:sec (Results 1 - 25 of 49) sorted by relevance

12

/gem5/util/cpt_upgraders/
H A Druby-block-size-bytes.py3 for sec in cpt.sections():
4 if sec == 'system.ruby':
7 cpt.set(sec, 'block_size_bytes', '64')
H A Dx86-add-tlb.py4 for sec in cpt.sections():
7 if re.search('.*sys.*\.cpu.*\.dtb$', sec):
8 cpt.set(sec, '_size', '0')
9 cpt.set(sec, 'lruSeq', '0')
11 if re.search('.*sys.*\.cpu.*\.itb$', sec):
12 cpt.set(sec, '_size', '0')
13 cpt.set(sec, 'lruSeq', '0')
H A Dide-dma-abort.py3 for sec in cpt.sections():
5 if cpt.has_option(sec, "curSector"):
6 cpt.set(sec, "dmaAborted", "false")
H A Dcpu-pid.py2 for sec in cpt.sections():
5 if re.search('.*sys.*cpu', sec):
7 junk = cpt.get(sec, 'instCnt')
8 cpt.set(sec, '_pid', '0')
H A Dmemory-per-range.py5 for sec in cpt.sections():
8 if re.search('.*sys.*\.physmem$', sec):
10 cpt.set(sec, 'nbr_of_stores', '1')
14 mem_filename = cpt.get(sec, 'filename')
15 mem_size = cpt.get(sec, '_size')
16 cpt.remove_option(sec, 'filename')
17 cpt.remove_option(sec, '_size')
20 system_name = str(sec).split('.')[0]
26 elif re.search('.*sys.*\.\w*mem$', sec):
30 raise ValueError("more than one memory detected (" + sec
[all...]
H A Ddvfs-perflevel.py3 for sec in cpt.sections():
6 if re.match('^.*sys.*[._]clk_domain$', sec):
8 cpt.set(sec, '_perfLevel', ' '.join('0'))
9 elif re.match('^.*sys.*[._]voltage_domain$', sec):
11 cpt.set(sec, '_perfLevel', ' '.join('0'))
H A Dsmt-interrupts.py5 for sec in cpt.sections():
8 re_cpu_match = re.match('^(.*sys.*\.cpu[^._]*)$', sec)
10 interrupts = cpt.get(sec, 'interrupts')
11 intStatus = cpt.get(sec, 'intStatus')
18 cpt.remove_option(sec, 'interrupts')
19 cpt.remove_option(sec, 'intStatus')
H A Darm-contextidr-el2.py4 for sec in cpt.sections():
7 if re.search('.*sys.*\.cpu.*\.isa$', sec):
8 miscRegs = cpt.get(sec, 'miscRegs').split()
11 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in miscRegs))
H A Darm-miscreg-teehbr.py4 for sec in cpt.sections():
7 if re.search('.*sys.*\.cpu.*\.isa$', sec):
8 mr = cpt.get(sec, 'miscRegs').split()
13 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
H A Dremove-arm-cpsr-mode-miscreg.py4 for sec in cpt.sections():
7 if re.search('.*sys.*\.cpu.*\.isa$', sec):
8 mr = cpt.get(sec, 'miscRegs').split()
11 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
H A Darm-gicv2-banked-regs.py39 for sec in cpt.sections():
42 if not re.search('\.gic$', sec):
44 cpuEnabled = cpt.get(sec, 'cpuEnabled' ).split()
46 intEnabled = cpt.get(sec, 'intEnabled' ).split()
47 pendingInt = cpt.get(sec, 'pendingInt' ).split()
48 activeInt = cpt.get(sec, 'activeInt' ).split()
49 intPriority = cpt.get(sec, 'intPriority').split()
50 cpuTarget = cpt.get(sec, 'cpuTarget' ).split()
62 cpt.set(sec, 'intEnabled', ' '.join(intEnabled))
63 cpt.set(sec, 'pendingIn
[all...]
H A Disa-is-simobject.py25 for sec in cpt.sections():
28 re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
41 for (key, value) in cpt.items(sec, raw=True):
49 cpt.remove_option(sec, key)
51 for (sec, options) in isa_sections:
55 if not cpt.has_section(sec):
56 cpt.add_section(sec)
58 if cpt.items(sec):
63 cpt.set(sec, key, value)
H A Darm-ccregs.py5 for sec in cpt.sections():
8 re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
14 for (item,value) in cpt.items(sec):
17 intRegs = cpt.get(sec, 'intRegs').split()
25 cpt.set(sec, 'intRegs', ' '.join(intRegs))
26 cpt.set(sec, 'ccRegs', ' '.join(ccRegs))
H A Darm-sve.py11 for sec in cpt.sections():
14 if re.search('.*sys.*\.cpu.*\.isa$', sec):
17 cpt.set(sec, 'haveSVE', 'false')
21 cpt.set(sec, 'sveVL', '1')
24 mr = cpt.get(sec, 'miscRegs').split()
35 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
H A Darm-gem5-gic-ext.py67 for sec in cpt.sections():
68 if re.search('.*\.gic$', sec):
70 value = cpt.get(sec, reg).split(" ")
74 cpt.set(sec, reg, " ".join(value))
77 cpt.set(sec, reg, " ".join([ default, ] * new_cpu_max))
H A Darmv8.py11 for sec in cpt.sections():
12 re_xc_match = re.match('^.*?sys.*?\.cpu(\d+)*\.xc\.*', sec)
17 fpr = cpt.get(sec, 'floatRegs.i').split()
26 cpt.set(sec, 'floatRegs.i', ' '.join(str(x) for x in fpr))
28 ir = cpt.get(sec, 'intRegs').split()
34 cpt.set(sec, 'intRegs', ' '.join(str(x) for x in ir))
37 for sec in cpt.sections():
38 re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*$", sec)
42 irqs = cpt.get(sec, "interrupts").split()
45 cpt.set(sec, "interrupt
[all...]
H A Detherswitch.py2 for sec in cpt.sections():
3 if sec == "system":
4 options = cpt.items(sec)
22 cpt.remove_option(sec, it[0])
H A Darm-hdlcd-upgrade.py76 for sec in cpt.sections():
77 if re.search('.*\.hdlcd$', sec):
80 options[new] = cpt.get(sec, old)
82 cpt.remove_section(sec)
83 cpt.add_section(sec)
85 cpt.set(sec, key, value)
90 sec_dma = "%s.dmaEngine" % sec
H A Dprocess-fdmap-rename.py13 for sec in cpt.sections():
16 if re.match('.*\.%s.*' % fdm, sec):
17 rename = re.sub(fdm, fde, sec)
21 rename_section(cpt, sec, rename)
H A Darm-sysreg-mapping-ns.py39 for sec in cpt.sections():
42 if re.search('.*sys.*\.cpu.*\.isa\d*$', sec):
43 mr = cpt.get(sec, 'miscRegs').split()
72 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
/gem5/src/base/
H A Dtime.hh65 explicit Time(double sec) { operator=(sec); } argument
67 Time(uint64_t sec, uint64_t nsec) { set(sec, nsec); } argument
74 time_t sec() const { return _time.tv_sec; } function in class:Time
79 void sec(time_t sec) { _time.tv_sec = sec; } argument
103 void set(time_t _sec, long _nsec) { sec(_sec); nsec(_nsec); }
120 sec(othe
[all...]
H A Dtime.cc69 return sec() * SimClock::Frequency +
76 time_t sec = this->sec(); local
81 ctime_r(&sec, buf, sizeof(buf));
83 ctime_r(&sec, buf);
89 struct tm *tm = localtime(&sec);
127 paramOut(cp, base + ".sec", sec());
136 paramIn(cp, base + ".sec", secs);
138 sec(sec
[all...]
/gem5/util/
H A Dcheckpoint_aggregator.py67 for sec in config.sections():
68 if re.compile("cpu").search(sec):
69 newsec = re.sub("cpu", "cpu" + str(i).zfill(num_digits), sec)
72 items = config.items(sec)
79 if re.compile("workload.FdMap256$").search(sec):
82 elif sec == "system":
84 elif sec == "Globals":
85 tick = config.getint(sec, "curTick")
90 merged_config.add_section(sec)
91 for item in config.items(sec)
[all...]
/gem5/src/base/loader/
H A Dobject_file.cc76 ObjectFile::loadSection(Section *sec, const PortProxy& mem_proxy, argument
79 if (sec->size != 0) {
80 Addr addr = (sec->baseAddr & addr_mask) + offset;
81 if (sec->fileImage) {
82 mem_proxy.writeBlob(addr, sec->fileImage, sec->size);
86 mem_proxy.memsetBlob(addr, 0, sec->size);
/gem5/src/dev/
H A Dmc146818.cc76 sec = time.tm_sec;
90 sec = bcdize(sec);
145 curTime.tm_sec = unbcdize(sec);

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