111768SCurtis.Dunham@arm.com# Copyright (c) 2016 ARM Limited
211768SCurtis.Dunham@arm.com# All rights reserved
311768SCurtis.Dunham@arm.com#
411768SCurtis.Dunham@arm.com# The license below extends only to copyright in the software and shall
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611768SCurtis.Dunham@arm.com# property including but not limited to intellectual property relating
711768SCurtis.Dunham@arm.com# to a hardware implementation of the functionality of the software
811768SCurtis.Dunham@arm.com# licensed hereunder.  You may use the software subject to the license
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1011768SCurtis.Dunham@arm.com# unmodified and in its entirety in all distributions of the software,
1111768SCurtis.Dunham@arm.com# modified or unmodified, in source code or in binary form.
1211768SCurtis.Dunham@arm.com#
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1411768SCurtis.Dunham@arm.com# modification, are permitted provided that the following conditions are
1511768SCurtis.Dunham@arm.com# met: redistributions of source code must retain the above copyright
1611768SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer;
1711768SCurtis.Dunham@arm.com# redistributions in binary form must reproduce the above copyright
1811768SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer in the
1911768SCurtis.Dunham@arm.com# documentation and/or other materials provided with the distribution;
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2211768SCurtis.Dunham@arm.com# this software without specific prior written permission.
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2411768SCurtis.Dunham@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2511768SCurtis.Dunham@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
2611768SCurtis.Dunham@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2711768SCurtis.Dunham@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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3311768SCurtis.Dunham@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3411768SCurtis.Dunham@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3511768SCurtis.Dunham@arm.com
3611768SCurtis.Dunham@arm.com# reflect updated register mappings for ARM ISA
3711768SCurtis.Dunham@arm.comdef upgrader(cpt):
3811768SCurtis.Dunham@arm.com    if cpt.get('root','isa') == 'arm':
3911768SCurtis.Dunham@arm.com        for sec in cpt.sections():
4011768SCurtis.Dunham@arm.com            import re
4111768SCurtis.Dunham@arm.com            # Search for all ISA sections
4211768SCurtis.Dunham@arm.com            if re.search('.*sys.*\.cpu.*\.isa\d*$', sec):
4311768SCurtis.Dunham@arm.com                mr = cpt.get(sec, 'miscRegs').split()
4411768SCurtis.Dunham@arm.com                if int(mr[0]) & 16 == 0: # CPSR reg width; 0 for AArch64
4511768SCurtis.Dunham@arm.com                    mr[112] = mr[111] # ACTLR_NS = ACTLR
4611768SCurtis.Dunham@arm.com                    mr[146] = mr[145] # ADFSR_NS = ADFSR
4711768SCurtis.Dunham@arm.com                    mr[149] = mr[148] # AIFSR_NS = AIFSR
4811768SCurtis.Dunham@arm.com                    mr[253] = mr[252] # AMAIR0_NS = AMAIR0
4911768SCurtis.Dunham@arm.com                    mr[289] = mr[288] # CNTP_CTL_NS = CNTP_CTL
5011768SCurtis.Dunham@arm.com                    mr[313] = mr[312] # CNTP_CVAL_NS = CNTP_CVAL
5111768SCurtis.Dunham@arm.com                    mr[286] = mr[285] # CNTP_TVAL_NS = CNTP_TVAL
5211768SCurtis.Dunham@arm.com                    mr[271] = mr[270] # CONTEXTIDR_NS = CONTEXTIDR
5311768SCurtis.Dunham@arm.com                    mr[104] = mr[103] # CSSELR_NS = CSSELR
5411768SCurtis.Dunham@arm.com                    mr[137] = mr[136] # DACR_NS = DACR
5511768SCurtis.Dunham@arm.com                    mr[155] = mr[154] # DFAR_NS = DFAR
5611768SCurtis.Dunham@arm.com                    mr[158] = mr[157] # IFAR_NS = IFAR
5711768SCurtis.Dunham@arm.com                    mr[143] = mr[142] # IFSR_NS = IFSR
5811768SCurtis.Dunham@arm.com                    mr[247] = mr[246] # NMRR_NS = NMRR
5911768SCurtis.Dunham@arm.com                    mr[166] = mr[165] # PAR_NS = PAR
6011768SCurtis.Dunham@arm.com                    mr[241] = mr[240] # PRRR_NS = PRRR
6111768SCurtis.Dunham@arm.com                    mr[  4] = mr[424] # SPSR_SVC = SPSR_EL1
6211768SCurtis.Dunham@arm.com                    mr[  7] = mr[435] # SPSR_HYP = SPSR_EL2
6311768SCurtis.Dunham@arm.com                    mr[  5] = mr[442] # SPSR_MON = SPSR_EL3
6411768SCurtis.Dunham@arm.com                    mr[277] = mr[276] # TPIDRURO_NS = TPIDRURO
6511768SCurtis.Dunham@arm.com                    mr[280] = mr[279] # TPIDRPRW_NS = TPIDRPRW
6611768SCurtis.Dunham@arm.com                    mr[274] = mr[273] # TPIDRURW_NS = TPIDRURW
6711768SCurtis.Dunham@arm.com                    mr[132] = mr[131] # TTBCR_NS = TTBCR
6811768SCurtis.Dunham@arm.com                    mr[126] = mr[125] # TTBR0_NS = TTBR0
6911768SCurtis.Dunham@arm.com                    mr[129] = mr[128] # TTBR1_NS = TTBR1
7011768SCurtis.Dunham@arm.com                    mr[263] = mr[262] # VBAR_NS = VBAR
7111768SCurtis.Dunham@arm.com
7211768SCurtis.Dunham@arm.com                    cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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