1# Add all ARMv8 state
2def upgrader(cpt):
3    if cpt.get('root','isa') != 'arm':
4        return
5    import re
6    print "Warning: The size of the FP register file has changed. "\
7          "To get similar results you need to adjust the number of "\
8          "physical registers in the CPU you're restoring into by "\
9          "NNNN."
10    # Find the CPU context's and upgrade their registers
11    for sec in cpt.sections():
12        re_xc_match = re.match('^.*?sys.*?\.cpu(\d+)*\.xc\.*', sec)
13        if not re_xc_match:
14            continue
15
16        # Update floating point regs
17        fpr = cpt.get(sec, 'floatRegs.i').split()
18        # v8 has 128 normal fp and 32 special fp regs compared
19        # to v7's 64 normal fp and 8 special fp regs.
20        # Insert the extra normal fp registers at end of v7 normal fp regs
21        for x in xrange(64):
22            fpr.insert(64, "0")
23        # Append the extra special registers
24        for x in xrange(24):
25            fpr.append("0")
26        cpt.set(sec, 'floatRegs.i', ' '.join(str(x) for x in fpr))
27
28        ir = cpt.get(sec, 'intRegs').split()
29        # Add in v8 int reg state
30        # Splice in R13_HYP
31        ir.insert(20, "0")
32        # Splice in INTREG_DUMMY and SP0 - SP3
33        ir.extend(["0", "0", "0", "0", "0"])
34        cpt.set(sec, 'intRegs', ' '.join(str(x) for x in ir))
35
36    # Update the cpu interrupt field
37    for sec in cpt.sections():
38        re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*$", sec)
39        if not re_int_match:
40            continue
41
42        irqs = cpt.get(sec, "interrupts").split()
43        irqs.append("false")
44        irqs.append("false")
45        cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs))
46
47    # Update the per cpu interrupt structure
48    for sec in cpt.sections():
49        re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*\.interrupts$", sec)
50        if not re_int_match:
51            continue
52
53        irqs = cpt.get(sec, "interrupts").split()
54        irqs.append("false")
55        irqs.append("false")
56        cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs))
57
58    # Update the misc regs and add in new isa specific fields
59    for sec in cpt.sections():
60        re_isa_match = re.match("^.*?sys.*?\.cpu(\d+)*\.isa$", sec)
61        if not re_isa_match:
62            continue
63
64        cpt.set(sec, 'haveSecurity', 'false')
65        cpt.set(sec, 'haveLPAE', 'false')
66        cpt.set(sec, 'haveVirtualization', 'false')
67        cpt.set(sec, 'haveLargeAsid64', 'false')
68        cpt.set(sec, 'physAddrRange64', '40')
69
70        # splice in the new misc registers, ~200 -> 605 registers,
71        # ordering does not remain consistent
72        mr_old = cpt.get(sec, 'miscRegs').split()
73        mr_new = [ '0' for x in xrange(605) ]
74
75        # map old v7 miscRegs to new v8 miscRegs
76        mr_new[0] = mr_old[0] # CPSR
77        mr_new[16] = mr_old[1] # CPSR_Q
78        mr_new[1] = mr_old[2] # SPSR
79        mr_new[2] = mr_old[3] # SPSR_FIQ
80        mr_new[3] = mr_old[4] # SPSR_IRQ
81        mr_new[4] = mr_old[5] # SPSR_SVC
82        mr_new[5] = mr_old[6] # SPSR_MON
83        mr_new[8] = mr_old[7] # SPSR_UND
84        mr_new[6] = mr_old[8] # SPSR_ABT
85        mr_new[432] = mr_old[9] # FPSR
86        mr_new[10] = mr_old[10] # FPSID
87        mr_new[11] = mr_old[11] # FPSCR
88        mr_new[18] = mr_old[12] # FPSCR_QC
89        mr_new[17] = mr_old[13] # FPSCR_EXC
90        mr_new[14] = mr_old[14] # FPEXC
91        mr_new[13] = mr_old[15] # MVFR0
92        mr_new[12] = mr_old[16] # MVFR1
93        mr_new[28] = mr_old[17] # SCTLR_RST,
94        mr_new[29] = mr_old[18] # SEV_MAILBOX,
95        mr_new[30] = mr_old[19] # DBGDIDR
96        mr_new[31] = mr_old[20] # DBGDSCR_INT,
97        mr_new[33] = mr_old[21] # DBGDTRRX_INT,
98        mr_new[34] = mr_old[22] # DBGTRTX_INT,
99        mr_new[35] = mr_old[23] # DBGWFAR,
100        mr_new[36] = mr_old[24] # DBGVCR,
101        #mr_new[] = mr_old[25] # DBGECR -> UNUSED,
102        #mr_new[] = mr_old[26] # DBGDSCCR -> UNUSED,
103        #mr_new[] = mr_old[27] # DBGSMCR -> UNUSED,
104        mr_new[37] = mr_old[28] # DBGDTRRX_EXT,
105        mr_new[38] = mr_old[29] # DBGDSCR_EXT,
106        mr_new[39] = mr_old[30] # DBGDTRTX_EXT,
107        #mr_new[] = mr_old[31] # DBGDRCR -> UNUSED,
108        mr_new[41] = mr_old[32] # DBGBVR,
109        mr_new[47] = mr_old[33] # DBGBCR,
110        #mr_new[] = mr_old[34] # DBGBVR_M -> UNUSED,
111        #mr_new[] = mr_old[35] # DBGBCR_M -> UNUSED,
112        mr_new[61] = mr_old[36] # DBGDRAR,
113        #mr_new[] = mr_old[37] # DBGBXVR_M -> UNUSED,
114        mr_new[64] = mr_old[38] # DBGOSLAR,
115        #mr_new[] = mr_old[39] # DBGOSSRR -> UNUSED,
116        mr_new[66] = mr_old[40] # DBGOSDLR,
117        mr_new[67] = mr_old[41] # DBGPRCR,
118        #mr_new[] = mr_old[42] # DBGPRSR -> UNUSED,
119        mr_new[68] = mr_old[43] # DBGDSAR,
120        #mr_new[] = mr_old[44] # DBGITCTRL -> UNUSED,
121        mr_new[69] = mr_old[45] # DBGCLAIMSET,
122        mr_new[70] = mr_old[46] # DBGCLAIMCLR,
123        mr_new[71] = mr_old[47] # DBGAUTHSTATUS,
124        mr_new[72] = mr_old[48] # DBGDEVID2,
125        mr_new[73] = mr_old[49] # DBGDEVID1,
126        mr_new[74] = mr_old[50] # DBGDEVID,
127        mr_new[77] = mr_old[51] # TEEHBR,
128        mr_new[109] = mr_old[52] # v7 SCTLR -> aarc32 SCTLR_NS
129        mr_new[189] = mr_old[53] # DCCISW,
130        mr_new[188] = mr_old[54] # DCCIMVAC,
131        mr_new[183] = mr_old[55] # DCCMVAC,
132        mr_new[271] = mr_old[56] # v7 CONTEXTIDR -> aarch32 CONTEXTIDR_NS,
133        mr_new[274] = mr_old[57] # v7 TPIDRURW -> aarch32 TPIDRURW_NS,
134        mr_new[277] = mr_old[58] # v7 TPIDRURO -> aarch32 TPIDRURO_NS,
135        mr_new[280] = mr_old[59] # v7 TPIDRPRW -> aarch32 TPIDRPRW_NS,
136        mr_new[170] = mr_old[60] # CP15ISB,
137        mr_new[185] = mr_old[61] # CP15DSB,
138        mr_new[186] = mr_old[62] # CP15DMB,
139        mr_new[114] = mr_old[63] # CPACR,
140        mr_new[101] = mr_old[64] # CLIDR,
141        mr_new[100] = mr_old[65] # CCSIDR,
142        mr_new[104] = mr_old[66] # v7 CSSELR -> aarch32 CSSELR_NS,
143        mr_new[163] = mr_old[67] # ICIALLUIS,
144        mr_new[168] = mr_old[68] # ICIALLU,
145        mr_new[169] = mr_old[69] # ICIMVAU,
146        mr_new[172] = mr_old[70] # BPIMVA,
147        mr_new[164] = mr_old[71] # BPIALLIS,
148        mr_new[171] = mr_old[72] # BPIALL,
149        mr_new[80] = mr_old[73] # MIDR,
150        mr_new[126] = mr_old[74] # v7 TTBR0 -> aarch32 TTBR0_NS,
151        mr_new[129] = mr_old[75] # v7 TTBR1 -> aarch32 TTBR1_NS,
152        mr_new[83] = mr_old[76] # TLBTR,
153        mr_new[137] = mr_old[77] # v7 DACR -> aarch32 DACR_NS,
154        mr_new[192] = mr_old[78] # TLBIALLIS,
155        mr_new[193] = mr_old[79] # TLBIMVAIS,
156        mr_new[194] = mr_old[80] # TLBIASIDIS,
157        mr_new[195] = mr_old[81] # TLBIMVAAIS,
158        mr_new[198] = mr_old[82] # ITLBIALL,
159        mr_new[199] = mr_old[83] # ITLBIMVA,
160        mr_new[200] = mr_old[84] # ITLBIASID,
161        mr_new[201] = mr_old[85] # DTLBIALL,
162        mr_new[202] = mr_old[86] # DTLBIMVA,
163        mr_new[203] = mr_old[87] # DTLBIASID,
164        mr_new[204] = mr_old[88] # TLBIALL,
165        mr_new[205] = mr_old[89] # TLBIMVA,
166        mr_new[206] = mr_old[90] # TLBIASID,
167        mr_new[207] = mr_old[91] # TLBIMVAA,
168        mr_new[140] = mr_old[92] # v7 DFSR -> aarch32 DFSR_NS,
169        mr_new[143] = mr_old[93] # v7 IFSR -> aarch32 IFSR_NS,
170        mr_new[155] = mr_old[94] # v7 DFAR -> aarch32 DFAR_NS,
171        mr_new[158] = mr_old[95] # v7 IFAR -> aarch32 IFAR_NS,
172        mr_new[84] = mr_old[96] # MPIDR,
173        mr_new[241] = mr_old[97] # v7 PRRR -> aarch32 PRRR_NS,
174        mr_new[247] = mr_old[98] # v7 NMRR -> aarch32 NMRR_NS,
175        mr_new[131] = mr_old[99] # TTBCR,
176        mr_new[86] = mr_old[100] # ID_PFR0,
177        mr_new[81] = mr_old[101] # CTR,
178        mr_new[115] = mr_old[102] # SCR,
179        # Set the non-secure bit
180        scr = int(mr_new[115])
181        scr = scr | 0x1
182        mr_new[115] = str(scr)
183        ###
184        mr_new[116] = mr_old[103] # SDER,
185        mr_new[165] = mr_old[104] # PAR,
186        mr_new[175] = mr_old[105] # V2PCWPR -> ATS1CPR,
187        mr_new[176] = mr_old[106] # V2PCWPW -> ATS1CPW,
188        mr_new[177] = mr_old[107] # V2PCWUR -> ATS1CUR,
189        mr_new[178] = mr_old[108] # V2PCWUW -> ATS1CUW,
190        mr_new[179] = mr_old[109] # V2POWPR -> ATS12NSOPR,
191        mr_new[180] = mr_old[110] # V2POWPW -> ATS12NSOPW,
192        mr_new[181] = mr_old[111] # V2POWUR -> ATS12NSOUR,
193        mr_new[182] = mr_old[112] # V2POWUW -> ATS12NWOUW,
194        mr_new[90] = mr_old[113] # ID_MMFR0,
195        mr_new[92] = mr_old[114] # ID_MMFR2,
196        mr_new[93] = mr_old[115] # ID_MMFR3,
197        mr_new[112] = mr_old[116] # v7 ACTLR -> aarch32 ACTLR_NS
198        mr_new[222] = mr_old[117] # PMCR,
199        mr_new[230] = mr_old[118] # PMCCNTR,
200        mr_new[223] = mr_old[119] # PMCNTENSET,
201        mr_new[224] = mr_old[120] # PMCNTENCLR,
202        mr_new[225] = mr_old[121] # PMOVSR,
203        mr_new[226] = mr_old[122] # PMSWINC,
204        mr_new[227] = mr_old[123] # PMSELR,
205        mr_new[228] = mr_old[124] # PMCEID0,
206        mr_new[229] = mr_old[125] # PMCEID1,
207        mr_new[231] = mr_old[126] # PMXEVTYPER,
208        mr_new[233] = mr_old[127] # PMXEVCNTR,
209        mr_new[234] = mr_old[128] # PMUSERENR,
210        mr_new[235] = mr_old[129] # PMINTENSET,
211        mr_new[236] = mr_old[130] # PMINTENCLR,
212        mr_new[94] = mr_old[131] # ID_ISAR0,
213        mr_new[95] = mr_old[132] # ID_ISAR1,
214        mr_new[96] = mr_old[133] # ID_ISAR2,
215        mr_new[97] = mr_old[134] # ID_ISAR3,
216        mr_new[98] = mr_old[135] # ID_ISAR4,
217        mr_new[99] = mr_old[136] # ID_ISAR5,
218        mr_new[20] = mr_old[137] # LOCKFLAG,
219        mr_new[19] = mr_old[138] # LOCKADDR,
220        mr_new[87] = mr_old[139] # ID_PFR1,
221        # Set up the processor features register
222        pfr = int(mr_new[87])
223        pfr = pfr | 0x1011
224        mr_new[87] = str(pfr)
225        ###
226        mr_new[238] = mr_old[140] # L2CTLR,
227        mr_new[82] = mr_old[141] # TCMTR
228        mr_new[88] = mr_old[142] # ID_DFR0,
229        mr_new[89] = mr_old[143] # ID_AFR0,
230        mr_new[91] = mr_old[144] # ID_MMFR1,
231        mr_new[102] = mr_old[145] # AIDR,
232        mr_new[146] = mr_old[146] # v7 ADFSR -> aarch32 ADFSR_NS,
233        mr_new[148] = mr_old[147] # AIFSR,
234        mr_new[173] = mr_old[148] # DCIMVAC,
235        mr_new[174] = mr_old[149] # DCISW,
236        mr_new[184] = mr_old[150] # MCCSW -> DCCSW,
237        mr_new[187] = mr_old[151] # DCCMVAU,
238        mr_new[117] = mr_old[152] # NSACR,
239        mr_new[262] = mr_old[153] # VBAR,
240        mr_new[265] = mr_old[154] # MVBAR,
241        mr_new[267] = mr_old[155] # ISR,
242        mr_new[269] = mr_old[156] # FCEIDR -> FCSEIDR,
243        #mr_new[] = mr_old[157] # L2LATENCY -> UNUSED,
244        #mr_new[] = mr_old[158] # CRN15 -> UNUSED,
245        mr_new[599] = mr_old[159] # NOP
246        mr_new[600] = mr_old[160] # RAZ,
247
248        # Set the new miscRegs structure
249        cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr_new))
250
251    cpu_prefix = {}
252    # Add in state for ITB/DTB
253    for sec in cpt.sections():
254        re_tlb_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb)$', sec)
255        if not re_tlb_match:
256            continue
257
258        cpu_prefix[re_tlb_match.group(1)] = True # Save off prefix to add
259        # Set the non-secure bit (bit 9) to 1 for attributes
260        attr = int(cpt.get(sec, '_attr'))
261        attr = attr | 0x200
262        cpt.set(sec, '_attr', str(attr))
263        cpt.set(sec, 'haveLPAE', 'false')
264        cpt.set(sec, 'directToStage2', 'false')
265        cpt.set(sec, 'stage2Req', 'false')
266        cpt.set(sec, 'bootUncacheability', 'true')
267
268    # Add in extra state for the new TLB Entries
269    for sec in cpt.sections():
270        re_tlbentry_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb).TlbEntry\d+$', sec)
271        if not re_tlbentry_match:
272            continue
273
274        # Add in the new entries
275        cpt.set(sec, 'longDescFormat', 'false')
276        cpt.set(sec, 'vmid', '0')
277        cpt.set(sec, 'isHyp', 'false')
278        valid = cpt.get(sec, 'valid')
279        if valid == 'true':
280            cpt.set(sec, 'ns', 'true')
281            cpt.set(sec, 'nstid', 'true')
282            cpt.set(sec, 'pxn', 'true')
283            cpt.set(sec, 'hap', '3')
284            # All v7 code used 2 level page tables
285            cpt.set(sec, 'lookupLevel', '2')
286            attr = int(cpt.get(sec, 'attributes'))
287            # set the non-secure bit (bit 9) to 1
288            # as no previous v7 code used secure code
289            attr = attr | 0x200
290            cpt.set(sec, 'attributes', str(attr))
291        else:
292            cpt.set(sec, 'ns', 'false')
293            cpt.set(sec, 'nstid', 'false')
294            cpt.set(sec, 'pxn', 'false')
295            cpt.set(sec, 'hap', '0')
296            cpt.set(sec, 'lookupLevel', '0')
297        cpt.set(sec, 'outerShareable', 'false')
298
299    # Add d/istage2_mmu and d/istage2_mmu.stage2_tlb
300    for key in cpu_prefix:
301        for suffix in ['.istage2_mmu', '.dstage2_mmu']:
302            new_sec = key + suffix
303            cpt.add_section(new_sec)
304            new_sec = key + suffix + ".stage2_tlb"
305            cpt.add_section(new_sec)
306            # Fill in tlb info with some defaults
307            cpt.set(new_sec, '_attr', '0')
308            cpt.set(new_sec, 'haveLPAE', 'false')
309            cpt.set(new_sec, 'directToStage2', 'false')
310            cpt.set(new_sec, 'stage2Req', 'false')
311            cpt.set(new_sec, 'bootUncacheability', 'false')
312            cpt.set(new_sec, 'num_entries', '0')
313
314legacy_version = 9
315