Searched refs:issued (Results 1 - 5 of 5) sorted by relevance

/gem5/src/cpu/o3/
H A Dstore_set.hh99 /** Records this PC/sequence number as issued. */
100 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
133 * not yet issued or squashed.
H A Dstore_set.cc274 StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
276 // This only is updated upon a store being issued.
293 // Make sure the SSIT still has a valid entry for the issued store.
303 // was just issued, then invalidate the entry.
H A Dmem_dep_unit_impl.hh557 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
/gem5/src/cpu/minor/
H A Dexecute.cc451 bool issued = false; local
453 /* Set to true if the mem op. is issued and sent to the mem system */
459 issued = false;
512 issued = true;
515 return issued;
555 /* Remains true while instructions are still being issued. If any
559 bool issued = true; local
579 issued = true;
586 issued = true;
592 issued
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H A Dlsq.cc866 bool issued = true; local
871 issued = false;
876 while (issued &&
890 issued = false;
902 * one hasn't issued all its packets as the store
904 issued = false;
1052 * not be speculatively issued and stores which must be issued here */
1218 /* Fully or partially issued a request in the transfers
1224 /* Fully or partially issued
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