| /gem5/src/arch/hsail/insts/ |
| H A D | gpu_static_inst.cc | 49 HsailGPUStaticInst::generateDisassembly() function in class:HsailISA::HsailGPUStaticInst
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| H A D | gpu_static_inst.hh | 57 void generateDisassembly() override;
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| /gem5/src/arch/sparc/insts/ |
| H A D | micro.cc | 37 SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::SparcMacroInst
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| H A D | mem.hh | 54 std::string generateDisassembly(
70 std::string generateDisassembly(
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| H A D | trap.hh | 59 std::string generateDisassembly(
71 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
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| H A D | priv.cc | 40 Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::Priv
50 RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::RdPriv
63 WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::WrPriv
83 WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::WrPrivImm
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| H A D | trap.cc | 38 Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::Trap
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| H A D | unknown.hh | 59 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
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| /gem5/src/arch/riscv/insts/ |
| H A D | compressed.hh | 51 std::string generateDisassembly(
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| H A D | mem.cc | 48 Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::Load
57 Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::Store
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| H A D | amo.hh | 55 std::string generateDisassembly(
65 std::string generateDisassembly(
75 std::string generateDisassembly(
85 std::string generateDisassembly(
95 std::string generateDisassembly(
105 std::string generateDisassembly(
115 std::string generateDisassembly(
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| H A D | amo.cc | 47 string MemFenceMicro::generateDisassembly(Addr pc, function in class:RiscvISA::MemFenceMicro
62 string LoadReserved::generateDisassembly(Addr pc, function in class:RiscvISA::LoadReserved
71 string LoadReservedMicro::generateDisassembly(Addr pc, function in class:RiscvISA::LoadReservedMicro
81 string StoreCond::generateDisassembly(Addr pc, function in class:RiscvISA::StoreCond
91 string StoreCondMicro::generateDisassembly(Addr pc, function in class:RiscvISA::StoreCondMicro
102 string AtomicMemOp::generateDisassembly(Addr pc, function in class:RiscvISA::AtomicMemOp
112 string AtomicMemOpMicro::generateDisassembly(Addr pc, function in class:RiscvISA::AtomicMemOpMicro
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| H A D | standard.hh | 53 std::string generateDisassembly(
80 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
101 std::string generateDisassembly(
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| H A D | mem.hh | 60 std::string generateDisassembly(
69 std::string generateDisassembly(
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| H A D | standard.cc | 47 RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::RegOp
57 CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::CSROp
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| H A D | compressed.cc | 44 CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::CompRegOp
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| /gem5/src/arch/power/insts/ |
| H A D | condition.cc | 36 CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:CondLogicOp
49 CondMoveOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:CondMoveOp
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| H A D | mem.cc | 38 MemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MemOp
44 MemDispOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MemDispOp
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| H A D | mem.hh | 56 std::string generateDisassembly(
76 std::string generateDisassembly(
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| H A D | floating.cc | 36 FloatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:FloatOp
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| H A D | misc.cc | 36 MiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MiscOp
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| H A D | misc.hh | 52 std::string generateDisassembly(
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| /gem5/src/arch/arm/insts/ |
| H A D | branch.cc | 47 BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::BranchReg
56 BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::BranchImm
65 BranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::BranchRegReg
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| H A D | misc.cc | 46 MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MrsOp
129 MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MsrImmOp
138 MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MsrRegOp
148 MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MrrcOp
161 McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:McrrOp
174 ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ImmOp
183 RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegImmOp
193 RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegRegOp
204 RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegRegRegImmOp
218 RegRegRegRegOp::generateDisassembly(Add function in class:RegRegRegRegOp
233 RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegRegRegOp
246 RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegRegImmOp
258 MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MiscRegRegImmOp
269 RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegMiscRegImmOp
280 RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegImmImmOp
290 RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegRegImmImmOp
302 RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegImmRegOp
313 RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RegImmRegShiftOp
325 UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:UnknownOp
353 McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:McrMrcMiscInst
379 McrMrcImplDefined::generateDisassembly(Addr pc, function in class:McrMrcImplDefined
[all...] |
| /gem5/src/arch/x86/insts/ |
| H A D | microfpop.cc | 56 std::string FpOp::generateDisassembly(Addr pc, function in class:X86ISA::FpOp
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