112320Sar4jc@virginia.edu/* 212320Sar4jc@virginia.edu * Copyright (c) 2015 RISC-V Foundation 312320Sar4jc@virginia.edu * Copyright (c) 2017 The University of Virginia 412320Sar4jc@virginia.edu * All rights reserved. 512320Sar4jc@virginia.edu * 612320Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 712320Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 812320Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 912320Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1012320Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1112320Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1212320Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1312320Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1412320Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1512320Sar4jc@virginia.edu * this software without specific prior written permission. 1612320Sar4jc@virginia.edu * 1712320Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812320Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912320Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012320Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112320Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212320Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312320Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412320Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512320Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612320Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712320Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812320Sar4jc@virginia.edu * 2912320Sar4jc@virginia.edu * Authors: Alec Roelke 3012320Sar4jc@virginia.edu */ 3112320Sar4jc@virginia.edu 3212320Sar4jc@virginia.edu#ifndef __ARCH_RISCV_STANDARD_INST_HH__ 3312320Sar4jc@virginia.edu#define __ARCH_RISCV_STANDARD_INST_HH__ 3412320Sar4jc@virginia.edu 3512320Sar4jc@virginia.edu#include <string> 3612320Sar4jc@virginia.edu 3712320Sar4jc@virginia.edu#include "arch/riscv/insts/bitfields.hh" 3812320Sar4jc@virginia.edu#include "arch/riscv/insts/static_inst.hh" 3912320Sar4jc@virginia.edu#include "cpu/exec_context.hh" 4012320Sar4jc@virginia.edu#include "cpu/static_inst.hh" 4112320Sar4jc@virginia.edu 4212320Sar4jc@virginia.edunamespace RiscvISA 4312320Sar4jc@virginia.edu{ 4412320Sar4jc@virginia.edu 4512320Sar4jc@virginia.edu/** 4612320Sar4jc@virginia.edu * Base class for operations that work only on registers 4712320Sar4jc@virginia.edu */ 4812320Sar4jc@virginia.educlass RegOp : public RiscvStaticInst 4912320Sar4jc@virginia.edu{ 5012320Sar4jc@virginia.edu protected: 5112320Sar4jc@virginia.edu using RiscvStaticInst::RiscvStaticInst; 5212320Sar4jc@virginia.edu 5312320Sar4jc@virginia.edu std::string generateDisassembly( 5412320Sar4jc@virginia.edu Addr pc, const SymbolTable *symtab) const override; 5512320Sar4jc@virginia.edu}; 5612320Sar4jc@virginia.edu 5712320Sar4jc@virginia.edu/** 5812320Sar4jc@virginia.edu * Base class for operations with immediates (I is the type of immediate) 5912320Sar4jc@virginia.edu */ 6012320Sar4jc@virginia.edutemplate<typename I> 6112320Sar4jc@virginia.educlass ImmOp : public RiscvStaticInst 6212320Sar4jc@virginia.edu{ 6312320Sar4jc@virginia.edu protected: 6412320Sar4jc@virginia.edu I imm; 6512320Sar4jc@virginia.edu 6612320Sar4jc@virginia.edu ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) 6712320Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass), imm(0) 6812320Sar4jc@virginia.edu {} 6912320Sar4jc@virginia.edu}; 7012320Sar4jc@virginia.edu 7112320Sar4jc@virginia.edu/** 7212320Sar4jc@virginia.edu * Base class for system operations 7312320Sar4jc@virginia.edu */ 7412320Sar4jc@virginia.educlass SystemOp : public RiscvStaticInst 7512320Sar4jc@virginia.edu{ 7612320Sar4jc@virginia.edu protected: 7712320Sar4jc@virginia.edu using RiscvStaticInst::RiscvStaticInst; 7812320Sar4jc@virginia.edu 7912320Sar4jc@virginia.edu std::string 8012320Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const override 8112320Sar4jc@virginia.edu { 8212320Sar4jc@virginia.edu return mnemonic; 8312320Sar4jc@virginia.edu } 8412320Sar4jc@virginia.edu}; 8512320Sar4jc@virginia.edu 8612320Sar4jc@virginia.edu/** 8712320Sar4jc@virginia.edu * Base class for CSR operations 8812320Sar4jc@virginia.edu */ 8912320Sar4jc@virginia.educlass CSROp : public RiscvStaticInst 9012320Sar4jc@virginia.edu{ 9112320Sar4jc@virginia.edu protected: 9212320Sar4jc@virginia.edu uint64_t csr; 9312320Sar4jc@virginia.edu uint64_t uimm; 9412320Sar4jc@virginia.edu 9512320Sar4jc@virginia.edu /// Constructor 9612320Sar4jc@virginia.edu CSROp(const char *mnem, MachInst _machInst, OpClass __opClass) 9712320Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass), 9812320Sar4jc@virginia.edu csr(FUNCT12), uimm(CSRIMM) 9912320Sar4jc@virginia.edu {} 10012320Sar4jc@virginia.edu 10112320Sar4jc@virginia.edu std::string generateDisassembly( 10212320Sar4jc@virginia.edu Addr pc, const SymbolTable *symtab) const override; 10312320Sar4jc@virginia.edu}; 10412320Sar4jc@virginia.edu 10512320Sar4jc@virginia.edu} 10612320Sar4jc@virginia.edu 10712320Sar4jc@virginia.edu#endif // __ARCH_RISCV_STANDARD_INST_HH__