Searched refs:deque (Results 1 - 25 of 59) sorted by relevance

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/gem5/src/doxygen/
H A Dstl.hh46 /** STL deque class */
47 template <class T> class deque { class in namespace:std
/gem5/src/systemc/ext/tlm_core/1/analysis/
H A Danalysis_port.hh24 #include <deque>
52 typename std::deque<tlm_analysis_if<T> *>::iterator i =
65 typename std::deque<tlm_analysis_if<T> *>::iterator i;
73 std::deque<tlm_analysis_if<T> *> m_interfaces;
/gem5/ext/systemc/src/tlm_core/tlm_1/tlm_analysis/
H A Dtlm_analysis_port.h24 #include <deque>
50 typename std::deque< tlm_analysis_if<T> * >::iterator i
63 typename std::deque< tlm_analysis_if<T> * >::iterator i;
76 std::deque< tlm_analysis_if<T> * > m_interfaces;
/gem5/src/dev/ps2/
H A Ddevice.hh47 #include <deque>
140 std::deque<uint8_t> outBuffer;
/gem5/src/dev/arm/
H A Drealview.cc49 #include <deque>
H A Dufs_device.hh147 #include <deque>
627 std::deque<struct SCSIResumeInfo> SCSIInfoQueue;
633 std::deque<struct transferInfo> SSDReadInfo;
641 std::deque<struct transferInfo> SSDWriteDoneInfo;
1088 std::deque<struct transferStart> transferEnd;
1099 std::deque<struct taskStart> taskInfo;
1100 std::deque<struct transferStart> transferStartInfo;
1105 std::deque<struct writeToDiskBurst> dmaWriteInfo;
1110 std::deque<struct transferInfo> SSDWriteinfo;
1115 std::deque<struc
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H A Dflash_device.hh42 #include <deque>
192 std::vector<std::deque<struct CallBackEntry> > planeEventQueue;
/gem5/src/mem/cache/prefetch/
H A Dpif.hh42 #include <deque>
124 std::deque<CompactorEntry> temporalCompactor;
149 std::deque<CompactorEntry*> streamAddressBuffer;
H A Dsbooe.hh40 #include <deque>
73 std::deque<Tick> latencyBuffer;
H A Dbop.hh91 std::deque<DelayQueueEntry> delayQueue;
/gem5/src/mem/
H A Dbridge.hh54 #include <deque>
125 * of the bridge. We use a deque as we need to iterate over
128 std::deque<DeferredPacket> transmitList;
242 * of the bridge. We use a deque as we need to iterate over
245 std::deque<DeferredPacket> transmitList;
H A Dserial_link.hh56 #include <deque>
121 * of the serial_link. We use a deque as we need to iterate over
124 std::deque<DeferredPacket> transmitList;
234 * of the serial_link. We use a deque as we need to iterate over
237 std::deque<DeferredPacket> transmitList;
H A Dxbar.hh54 #include <deque>
212 * A deque of ports that retry should be called on because
215 std::deque<SrcType*> waitingForLayer;
H A Ddramsim2.hh133 std::deque<PacketPtr> responseQueue;
/gem5/src/mem/qos/
H A Dq_policy.hh43 #include <deque>
62 typedef std::deque<PacketPtr> PacketQueue;
H A Dmem_sink.hh64 using PacketQueue = std::deque<PacketPtr>;
/gem5/src/dev/alpha/
H A Dtsunami.cc37 #include <deque>
/gem5/src/dev/mips/
H A Dmalta.cc38 #include <deque>
H A Dmalta_cchip.cc38 #include <deque>
/gem5/src/dev/sparc/
H A Dt1000.cc37 #include <deque>
H A Ddtod.cc38 #include <deque>
/gem5/src/cpu/pred/
H A Dsimple_indirect.hh34 #include <deque>
96 std::deque<HistoryEntry> pathHist;
/gem5/ext/pybind11/tests/
H A Dtest_stl_binders.cpp15 #include <deque>
82 py::bind_vector<std::deque<E_nc>>(m, "DequeENC");
83 m.def("get_dnc", &one_to_n<std::deque<E_nc>>, py::return_value_policy::reference);
/gem5/src/mem/ruby/network/garnet2.0/
H A DNetworkInterface.hh95 std::deque<flit *> m_stall_queue;
/gem5/src/dev/net/
H A Detherbus.cc37 #include <deque>

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