Searched refs:VecPredRegClass (Results 1 - 10 of 10) sorted by relevance

/gem5/src/cpu/o3/
H A Dfree_list.hh284 case VecPredRegClass:
317 case VecPredRegClass:
H A Drename_map.hh242 case VecPredRegClass:
285 case VecPredRegClass:
331 case VecPredRegClass:
H A Dregfile.cc118 vecPredRegIds.emplace_back(VecPredRegClass, phys_reg, flat_reg_idx++);
211 case VecPredRegClass:
H A Dcpu.cc285 renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
287 RegId(VecPredRegClass, ridx), phys_reg);
1372 RegId(VecPredRegClass, reg_idx));
1382 RegId(VecPredRegClass, reg_idx));
1445 RegId(VecPredRegClass, reg_idx));
H A Ddyn_inst.hh234 case VecPredRegClass:
H A Drename_impl.hh1090 case VecPredRegClass:
/gem5/src/cpu/
H A Dreg_class.hh63 VecPredRegClass, enumerator in enum:RegClass
161 bool isVecPredReg() const { return regClass == VecPredRegClass; }
191 case VecPredRegClass:
H A Dthread_context.cc93 RegId rid(VecPredRegClass, i);
/gem5/src/cpu/minor/
H A Dscoreboard.cc80 case VecPredRegClass:
/gem5/src/arch/arm/
H A Disa.hh461 case VecPredRegClass:
462 return RegId(VecPredRegClass,

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