| /gem5/src/learning_gem5/part2/ |
| H A D | SimpleMemobj.py | 37 inst_port = SlavePort("CPU side port, receives requests")
38 data_port = SlavePort("CPU side port, receives requests")
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| H A D | simple_memobj.hh | 53 class CPUSidePort : public SlavePort
70 SlavePort(name, owner), owner(owner), needRetry(false),
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| /gem5/src/mem/ |
| H A D | MemChecker.py | 52 slave = SlavePort("Slave port")
53 cpu_side = SlavePort("Alias for slave")
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| H A D | port.cc | 69 auto *slave_port = dynamic_cast<SlavePort *>(&peer);
114 SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id) function in class:SlavePort
120 SlavePort::~SlavePort()
125 SlavePort::slaveUnbind()
132 SlavePort::slaveBind(MasterPort& master_port)
139 SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
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| H A D | SimpleMemory.py | 48 port = SlavePort("Slave ports")
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| H A D | DRAMSim2.py | 47 port = SlavePort("Slave port")
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| H A D | Bridge.py | 48 slave = SlavePort('Slave port')
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| H A D | AddrMapper.py | 54 slave = SlavePort("Slave port")
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| H A D | MemDelay.py | 47 slave = SlavePort("Slave port")
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| H A D | ExternalSlave.py | 45 port = SlavePort("Slave port")
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| H A D | xbar.hh | 241 class ReqLayer : public Layer<SlavePort, MasterPort>
257 sendRetry(SlavePort* retry_port) override
263 class RespLayer : public Layer<MasterPort, SlavePort>
273 RespLayer(SlavePort& _port, BaseXBar& _xbar,
286 class SnoopRespLayer : public Layer<SlavePort, MasterPort>
304 sendRetry(SlavePort* retry_port) override
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| H A D | external_slave.hh | 53 * presentation of the SlavePort which can be bound.
55 * The external port must provide a gem5 SlavePort interface (with the
71 class ExternalPort : public SlavePort
79 SlavePort(name_, &owner_), owner(owner_)
92 * external port from gem5 and provide gem5 with a SlavePort that can be
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| H A D | SerialLink.py | 53 slave = SlavePort('Slave port')
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| H A D | snoop_filter.hh | 140 const SlavePort& slave_port);
170 * @param rsp_port SlavePort that sends the response.
171 * @param req_port SlavePort that made the original request and is the
174 void updateSnoopResponse(const Packet *cpkt, const SlavePort& rsp_port,
175 const SlavePort& req_port);
183 * @param rsp_port SlavePort that sends the response.
186 void updateSnoopForward(const Packet *cpkt, const SlavePort& rsp_port,
195 * @param slave_port SlavePort that made the original request and
198 void updateResponse(const Packet *cpkt, const SlavePort& slave_port);
244 * @param port SlavePort tha
[all...] |
| H A D | mem_delay.cc | 124 MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent) function in class:MemDelay::SlavePort
131 MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
139 MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
149 MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
159 MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
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| H A D | port.hh | 63 class SlavePort;
78 friend class SlavePort;
81 SlavePort *_slavePort;
250 * A SlavePort is a specialisation of a port. In addition to the
258 class SlavePort : public Port, public AtomicResponseProtocol, class in inherits:Port,AtomicResponseProtocol,TimingResponseProtocol,FunctionalResponseProtocol
271 SlavePort(const std::string& name, SimObject* _owner,
273 virtual ~SlavePort();
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| H A D | mem_delay.hh | 102 class SlavePort : public QueuedSlavePort class in class:MemDelay
105 SlavePort(const std::string &_name, MemDelay &_parent);
128 SlavePort slavePort;
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| H A D | qport.hh | 60 class QueuedSlavePort : public SlavePort
81 SlavePort(name, owner, id), respQueue(resp_queue)
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| H A D | packet_queue.hh | 304 SlavePort& slavePort;
308 static const std::string name(const SlavePort& slavePort,
324 RespPacketQueue(EventManager& _em, SlavePort& _slavePort,
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| /gem5/src/mem/qos/ |
| H A D | QoSMemSinkCtrl.py | 45 port = SlavePort("Slave ports")
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| /gem5/src/gpu-compute/ |
| H A D | LdsState.py | 49 cuPort = SlavePort("port that goes to the compute unit")
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| /gem5/src/mem/ruby/network/ |
| H A D | MessageBuffer.py | 46 slave = SlavePort("Slave port from MessageBuffer sender")
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| /gem5/src/arch/x86/ |
| H A D | X86LocalApic.py | 53 int_slave = SlavePort("Port for receiving interrupt messages")
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| /gem5/src/mem/ruby/system/ |
| H A D | Sequencer.py | 44 pio_slave_port = SlavePort("Ruby pio slave port")
45 mem_slave_port = SlavePort("Ruby memory port")
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | TlmBridge.py | 42 gem5 = SlavePort('gem5 slave port')
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